`write_rtlil` and `read_rtlil` won't recreate the same design

[wsipak]

Version

Yosys 0.24+1 (git sha1 1f6ac926a, gcc 12.2.1 -fPIC -Os)

On which OS did this happen?

Linux

Reproduction Steps

#!/bin/bash
TEST_DIR=operators
INPUT=yosys/tests/simple/operators.v

mkdir -p $TEST_DIR

# read verilog, generate RTLIL and netlist
yosys \
-p "read_verilog -sv $INPUT" \
-p "write_rtlil $TEST_DIR/yosys_rtlil.txt" \
-p "synth_xilinx" \
-p "write_verilog $TEST_DIR/yosys_gate.v"

# read RTLIL, generate netlist
yosys \
-p "read_rtlil $TEST_DIR/yosys_rtlil.txt" \
-p "synth_xilinx" \
-p "write_verilog $TEST_DIR/yosys_rtlil_gate.v"

operators/yosys_rtlil_gate.v and operators/yosys_gate.v differ.

Expected Behavior

It's expected, that when we generate a netlist using read_verilog , synth_xilinx, write_verilog, it will be the same as (or equivalent to) the netlist that is generated from RTLIL, assuming that the RTLIL is of the same exact design, as can bee seen in the script above.

Actual Behavior

The netlists differ, even though they were generated for the same exact test case.

[nakengelhardt]

Some of the passes (abc in particular) use heuristics that can produce differing results based on small changes (e.g. slightly different wire/cell names). Reloading the design changes some autoindex numbers and some pointer values that can change iteration order for set structures. We've tried to reduce these cases as much as possible but can't eliminate them entirely.

[povik]

I can reproduce, and have labeled the ticket a feature request since I don't think Yosys makes any guarantees of determinism, though it would be desirable.