Yosys Fails to Detect Syntax Violations According to Verilog Standards

[1353369570]

Version

Yosys 0.39+149

On which OS did this happen?

Linux

Reproduction Steps

I inadvertently created a design with a syntax error： when yosys-p "read_verilog ；synth; "

Expected Behavior

The yosys should synthesis failed as Vivado :

Actual Behavior

Yosys successfully synth pass；

[Ravenslofty]

I think the warnings demonstrate that Yosys is absolutely detecting the issues; it's just permissively accepting them.

For this, there is the -e option to Yosys:

    -e regex
        if a warning message matches the regex, it is printed as error
        message instead and the tool terminates with a nonzero return code.

[KrystalDelusion]

The read_verilog help explicitly says the following:

Note that the Verilog frontend does a pretty good job of processing valid verilog input, but has not very good error reporting. It generally is recommended to use a simulator (for example Icarus Verilog) for checking the syntax of the code, rather than to rely on read_verilog for that.

I think this is probably a wontfix situation.