Stub RTL Generation Feature

[Peter-Herrmann]

Feature Description

Designs frequently need to stub out modules to simplify simulation or synthesis during development. As part of workflows, it is very useful to be able to automatically generate stub modules from design files.   I would like to request a feature where Yosys can "stub-out" a module, similar to blackbox but with the ability to tie outputs to default values.

Bare Minimum Features

• Remove all internal logic (like blackbox)
• Tie all outputs to zero

Nice-to-have Features

• Configurable stub output behavior:
  • Selectively assign constants to outputs
  • Pass-through ports
  • Flop (N-cycle delay)

For example, to create a stub module for a module foo:

module foo (
    input  wire A_i,
    output wire B_o
);

    assign B_i = ~A_i;

endmodule

One could read in the file and use a command:

yosys> stub -set output_port_o 1 foo

Which would generate a module similar to this:

/* Generated by Yosys 0.39+147 (git sha1 0a854cf4c, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */

(* src = "foo.v:1.1-8.10" *)
module foo(A_i, B_o);
  (* src = "foo.v:2.17-2.20" *)
  input A_i;
  wire A_i;
  (* src = "foo.v:3.17-3.20" *)
  output B_o;
  wire B_o;
  assign B_o = 1'b1;
endmodule

Note the following differences from blackbox modules:

• Stub modules would not be marked with blackbox or cells_not_processed attributes
• All outputs are assigned