Open wyager opened 3 months ago
This is the same root cause as #4349 but instead of wire naming, it's cell naming.
In the Dev JF it was proposed that synthesis scripts call splitnets
for FPGAs, much like the external ASIC synthesis scripts do. That fixes #4349, and it also fixes this issue.
Hopefully I remember to submit a PR to that effect.
Version
Yosys 0.42+12 (git sha1 a55e8594b, aarch64-apple-darwin21.4-clang++ 14.0.0-1ubuntu1.1 -fPIC -Os)
On which OS did this happen?
macOS
Reproduction Steps
Download this zip file and run
run_me.sh
(not a virus, I promise) error-repro.zipI tried running with
-dff
per @Ravenslofty's suggestion, no diceExpected Behavior
yosys should synthesize something
Actual Behavior