Rules that need to be changed

yipengsun commented 6 years ago

[x] SDA and SCL are flipped. (need to change in both pigtail and dcb mapping Excel docs). Edit: I have updated the trueType mapping Excel to v5.2, and pushed the changes. - ZSY
[x] input/BrkOutBrd_Pin_Assignments_..._.xls needs to be completely updated, because Tom has changed almost everything related on the schematic. Tom did not update the Excel file, so we need to copy and paste from Altium. Not surprisingly, Altium's copy as text function does not preserve the order, so anticipate some hours wasted here. To check if telemetry JT pins changed. Edit: This has been updated by me and double-checked by Tom. (Did not find JT change, although Tom mentioned he'd add GND there are. But GND on JT should be transparent to mapping.) - ZSY
[x] THERMISTOR_N in Tom's list is connected to AGND (need to change our source code/change manually). This single DCB pin is connected to multiple PigTail pins (because AGND is on DCB). Edit: Tom agreed to leave this case for manual editing.
[x] A few cases of shortening THERMISTOR to THERM.
[x] naming inconsistency, Zishuo: JP0_UNUSED; Tom: GND; e.g. JP pins B29, C29, D29, E29, E34, I10 This means adding a rule that assign GND instead of UNUSED.
[x] naming inconsistency: for single-ended signals HYB_i2C/EC_RESET/EC_ADC, Tom appended _P to the signal ID. _Edit: This is addressed by adding a new rule, RulePT_PTSingleToDiff. For ECADC, Tom also added prefix THERM to signal ID
[x] Some naming inconsistencies for unconnected pins, expected since to be tied to GND. Using vim command :%s/Tom\: GND\; node\: DCB\: None//n, 514 out of 1085 warnings seem to be of this type. This is addressed by classifying Signal ID, and change their rules to give GND:
- - [x] _ASIC_: if unconnected, always ground
- - [x] _CLK_: if unconnected, always ground
- - [x] _TFC_: if unconnected, always ground
- - [x] _THERMISTOR_: if unconnected, always ground
- - [x] _I2C_ & _RESET_: if _P unconnected, always ground; if _P connected, _N need to connect to ??
- [x] For pins that are grayed-out in Excel (not used), they should always be GND. So we generalize the Unused rule to select Signal IDs with excel font_color.tint != 0.0, and make them GND.
[x] Tom has some JD_JP with no DCB pin, e.g.netlist name inconsistent: Zishuo: JP0_P1_EAST_I2C_SDA_N; Tom: JD2_JP0_EC_HYB_i2C_SDA_5_N; node: DCB: None, DCB_PIN: None, PT: JP0, PT_PIN: H9
[x] netlist name inconsistent: Zishuo: JP0_P1_WEST_RESET_N; Tom: JD0_JP0_EC_RESET_GPIO_5_N; node: DCB: None, DCB_PIN: None, PT: JP0, PT_PIN: I22
[x] ~~node in NET JD4_JP0_EC_ADC_5 not present in Tom's net: DCB: JD4, DCB_PIN: H42, PT: JP0, PT_PIN: C24. This is probably due to component entering between the nodes.~~ Edit: This is also caused by telemetry connection as below.
- [x] THERMISTOR_P assigned as e.g. JP0_JT0_P1_EAST_THERM_P by Tom, but as JD2H46_JP0J12_EC_ADC_7 by Zishuo This is due to the change of rule for some P_THERMISTOR: for 8-ASIC hybrids, the EAST of two thermistors is rerouted to JT telemetry board, e.g. JP1_JT0_P1_EAST_THERM_P, JP1_JT0_P1_EAST_THERM_P, JP0_JT0_P1_EAST_THERM_P. Specifically, for the original JD2H46-JP0J12 connection, because JP0J12=JP0_P1_EAST_THERM_P, now it's JP0J12-JT0XX and JD2H46_FRO. Proposed solution: change of rule to overwrite original connection, by matching JP + SigID on table JT in BrkOutBrd_Pin_Assignments.xlsx, and give ForReferenceOnly attribute to JD_EC_ADC pin. Edit: Tom agree to do this by hand.

error log after excluding understood types:

====ERRORS for Backplane connections====
========Not Implemented by Tom========
NOT present in Tom's net: NET: JD4_JP0_P2_EAST_THERMISTOR_N, NODE: DCB: JD4, DCB_PIN: H40, PT: JP0, PT_PIN: A5
NOT present in Tom's net: NET: JD4_JP0_P4_THERMISTOR_N, NODE: DCB: JD4, DCB_PIN: H40, PT: JP0, PT_PIN: B24
NOT present in Tom's net: NET: JD4_JP0_THERM_EC_ADC_5_P, NODE: DCB: JD4, DCB_PIN: H42, PT: JP0, PT_PIN: C24
NOT present in Tom's net: NET: JD4_JP0_P3_THERMISTOR_N, NODE: DCB: JD4, DCB_PIN: H40, PT: JP0, PT_PIN: E14
NOT present in Tom's net: NET: JD2_JP0_P1_EAST_THERMISTOR_N, NODE: DCB: JD2, DCB_PIN: H40, PT: JP0, PT_PIN: I12
NOT present in Tom's net: NET: JD0_JP0_P1_WEST_THERMISTOR_N, NODE: DCB: JD0, DCB_PIN: H40, PT: JP0, PT_PIN: I27
NOT present in Tom's net: NET: JD2_JP0_THERM_EC_ADC_7_P, NODE: DCB: JD2, DCB_PIN: H46, PT: JP0, PT_PIN: J12
NOT present in Tom's net: NET: JD0_JP1_P2_EAST_THERMISTOR_N, NODE: DCB: JD0, DCB_PIN: H40, PT: JP1, PT_PIN: A5
NOT present in Tom's net: NET: JD0_JP1_THERM_EC_ADC_3_P, NODE: DCB: JD0, DCB_PIN: H38, PT: JP1, PT_PIN: B5
NOT present in Tom's net: NET: JD4_JP1_P4_THERMISTOR_N, NODE: DCB: JD4, DCB_PIN: H40, PT: JP1, PT_PIN: B24
NOT present in Tom's net: NET: JD2_JP1_P2_WEST_THERMISTOR_N, NODE: DCB: JD2, DCB_PIN: H40, PT: JP1, PT_PIN: B40
NOT present in Tom's net: NET: JD4_JP1_P3_THERMISTOR_N, NODE: DCB: JD4, DCB_PIN: H40, PT: JP1, PT_PIN: E14
NOT present in Tom's net: NET: JD2_JP1_P1_EAST_THERMISTOR_N, NODE: DCB: JD2, DCB_PIN: H40, PT: JP1, PT_PIN: I12
NOT present in Tom's net: NET: JD0_JP1_P1_WEST_THERMISTOR_N, NODE: DCB: JD0, DCB_PIN: H40, PT: JP1, PT_PIN: I27
NOT present in Tom's net: NET: JD2_JP1_THERM_EC_ADC_5_P, NODE: DCB: JD2, DCB_PIN: H42, PT: JP1, PT_PIN: J12
NOT present in Tom's net: NET: JD1_JP2_P2_EAST_THERMISTOR_N, NODE: DCB: JD1, DCB_PIN: H40, PT: JP2, PT_PIN: A5
NOT present in Tom's net: NET: JD5_JP2_P4_THERMISTOR_N, NODE: DCB: JD5, DCB_PIN: H40, PT: JP2, PT_PIN: B24
NOT present in Tom's net: NET: JD3_JP2_P2_WEST_THERMISTOR_N, NODE: DCB: JD3, DCB_PIN: H40, PT: JP2, PT_PIN: B40
NOT present in Tom's net: NET: JD5_JP2_P3_THERMISTOR_N, NODE: DCB: JD5, DCB_PIN: H40, PT: JP2, PT_PIN: E14
NOT present in Tom's net: NET: JD3_JP2_P1_EAST_THERMISTOR_N, NODE: DCB: JD3, DCB_PIN: H40, PT: JP2, PT_PIN: I12
NOT present in Tom's net: NET: JD1_JP2_P1_WEST_THERMISTOR_N, NODE: DCB: JD1, DCB_PIN: H40, PT: JP2, PT_PIN: I27
NOT present in Tom's net: NET: JD5_JP3_P2_EAST_THERMISTOR_N, NODE: DCB: JD5, DCB_PIN: H40, PT: JP3, PT_PIN: A5
NOT present in Tom's net: NET: JD5_JP3_P4_THERMISTOR_N, NODE: DCB: JD5, DCB_PIN: H40, PT: JP3, PT_PIN: B24
NOT present in Tom's net: NET: JD5_JP3_P3_THERMISTOR_N, NODE: DCB: JD5, DCB_PIN: H40, PT: JP3, PT_PIN: E14
NOT present in Tom's net: NET: JD3_JP3_P1_EAST_THERMISTOR_N, NODE: DCB: JD3, DCB_PIN: H40, PT: JP3, PT_PIN: I12
NOT present in Tom's net: NET: JD1_JP3_P1_WEST_THERMISTOR_N, NODE: DCB: JD1, DCB_PIN: H40, PT: JP3, PT_PIN: I27
NOT present in Tom's net: NET: JD6_JP4_P2_EAST_THERMISTOR_N, NODE: DCB: JD6, DCB_PIN: H40, PT: JP4, PT_PIN: A5
NOT present in Tom's net: NET: JD8_JP4_P4_THERMISTOR_N, NODE: DCB: JD8, DCB_PIN: H40, PT: JP4, PT_PIN: B24
NOT present in Tom's net: NET: JD8_JP4_P3_THERMISTOR_N, NODE: DCB: JD8, DCB_PIN: H40, PT: JP4, PT_PIN: E14
NOT present in Tom's net: NET: JD6_JP4_P1_EAST_THERMISTOR_N, NODE: DCB: JD6, DCB_PIN: H40, PT: JP4, PT_PIN: I12
NOT present in Tom's net: NET: JD6_JP4_P1_WEST_THERMISTOR_N, NODE: DCB: JD6, DCB_PIN: H40, PT: JP4, PT_PIN: I27
NOT present in Tom's net: NET: JD8_JP5_P2_EAST_THERMISTOR_N, NODE: DCB: JD8, DCB_PIN: H40, PT: JP5, PT_PIN: A5
NOT present in Tom's net: NET: JD8_JP5_P3_THERMISTOR_N, NODE: DCB: JD8, DCB_PIN: H40, PT: JP5, PT_PIN: E14
NOT present in Tom's net: NET: JD4_JP5_P1_EAST_THERMISTOR_N, NODE: DCB: JD4, DCB_PIN: H40, PT: JP5, PT_PIN: I12
NOT present in Tom's net: NET: JD6_JP5_P1_WEST_THERMISTOR_N, NODE: DCB: JD6, DCB_PIN: H40, PT: JP5, PT_PIN: I27
NOT present in Tom's net: NET: JD9_JP6_P2_EAST_THERMISTOR_N, NODE: DCB: JD9, DCB_PIN: H40, PT: JP6, PT_PIN: A5
NOT present in Tom's net: NET: JD9_JP6_P3_THERMISTOR_N, NODE: DCB: JD9, DCB_PIN: H40, PT: JP6, PT_PIN: E14
NOT present in Tom's net: NET: JD5_JP6_P1_EAST_THERMISTOR_N, NODE: DCB: JD5, DCB_PIN: H40, PT: JP6, PT_PIN: I12
NOT present in Tom's net: NET: JD7_JP6_P1_WEST_THERMISTOR_N, NODE: DCB: JD7, DCB_PIN: H40, PT: JP6, PT_PIN: I27
NOT present in Tom's net: NET: JD7_JP7_P2_EAST_THERMISTOR_N, NODE: DCB: JD7, DCB_PIN: H40, PT: JP7, PT_PIN: A5
NOT present in Tom's net: NET: JD9_JP7_P4_THERMISTOR_N, NODE: DCB: JD9, DCB_PIN: H40, PT: JP7, PT_PIN: B24
NOT present in Tom's net: NET: JD9_JP7_P3_THERMISTOR_N, NODE: DCB: JD9, DCB_PIN: H40, PT: JP7, PT_PIN: E14
NOT present in Tom's net: NET: JD7_JP7_P1_EAST_THERMISTOR_N, NODE: DCB: JD7, DCB_PIN: H40, PT: JP7, PT_PIN: I12
NOT present in Tom's net: NET: JD7_JP7_P1_WEST_THERMISTOR_N, NODE: DCB: JD7, DCB_PIN: H40, PT: JP7, PT_PIN: I27
NOT present in Tom's net: NET: JD10_JP8_P2_EAST_THERMISTOR_N, NODE: DCB: JD10, DCB_PIN: H40, PT: JP8, PT_PIN: A5
NOT present in Tom's net: NET: JD10_JP8_P4_THERMISTOR_N, NODE: DCB: JD10, DCB_PIN: H40, PT: JP8, PT_PIN: B24
NOT present in Tom's net: NET: JD10_JP8_P3_THERMISTOR_N, NODE: DCB: JD10, DCB_PIN: H40, PT: JP8, PT_PIN: E14
NOT present in Tom's net: NET: JD8_JP8_P1_WEST_THERMISTOR_N, NODE: DCB: JD8, DCB_PIN: H40, PT: JP8, PT_PIN: I27
NOT present in Tom's net: NET: JD10_JP9_P2_EAST_THERMISTOR_N, NODE: DCB: JD10, DCB_PIN: H40, PT: JP9, PT_PIN: A5
NOT present in Tom's net: NET: JD10_JP9_P3_THERMISTOR_N, NODE: DCB: JD10, DCB_PIN: H40, PT: JP9, PT_PIN: E14
NOT present in Tom's net: NET: JD10_JP9_P1_WEST_THERMISTOR_N, NODE: DCB: JD10, DCB_PIN: H40, PT: JP9, PT_PIN: I27
NOT present in Tom's net: NET: JD11_JP10_P2_EAST_THERMISTOR_N, NODE: DCB: JD11, DCB_PIN: H40, PT: JP10, PT_PIN: A5
NOT present in Tom's net: NET: JD11_JP10_P3_THERMISTOR_N, NODE: DCB: JD11, DCB_PIN: H40, PT: JP10, PT_PIN: E14
NOT present in Tom's net: NET: JD11_JP10_P1_WEST_THERMISTOR_N, NODE: DCB: JD11, DCB_PIN: H40, PT: JP10, PT_PIN: I27
NOT present in Tom's net: NET: JD11_JP11_P2_EAST_THERMISTOR_N, NODE: DCB: JD11, DCB_PIN: H40, PT: JP11, PT_PIN: A5
NOT present in Tom's net: NET: JD11_JP11_P4_THERMISTOR_N, NODE: DCB: JD11, DCB_PIN: H40, PT: JP11, PT_PIN: B24
NOT present in Tom's net: NET: JD11_JP11_P3_THERMISTOR_N, NODE: DCB: JD11, DCB_PIN: H40, PT: JP11, PT_PIN: E14
NOT present in Tom's net: NET: JD9_JP11_P1_WEST_THERMISTOR_N, NODE: DCB: JD9, DCB_PIN: H40, PT: JP11, PT_PIN: I27

========DCB-None or None-PT========

========For Reference Only========

Not implemented telemetry:

NOT present in Tom's net: NET: JD4_JP0_THERM_EC_ADC_5_P, NODE: DCB: JD4, DCB_PIN: H42, PT: JP0, PT_PIN: C24
NOT present in Tom's net: NET: JD2_JP0_THERM_EC_ADC_7_P, NODE: DCB: JD2, DCB_PIN: H46, PT: JP0, PT_PIN: J12
NOT present in Tom's net: NET: JD0_JP1_THERM_EC_ADC_3_P, NODE: DCB: JD0, DCB_PIN: H38, PT: JP1, PT_PIN: B5
NOT present in Tom's net: NET: JD2_JP1_THERM_EC_ADC_5_P, NODE: DCB: JD2, DCB_PIN: H42, PT: JP1, PT_PIN: J12

ZishuoYang commented 6 years ago

Warning: Altium's "copy as text" function does not preserve the order of a group of Signal texts. This could lead to assigning wrong pins.

ZishuoYang commented 6 years ago

Some inconsistencies found by SchematicCheck.py that do not concern rule-changing:

[x] n P_LV_RETURN get tied together on JPU/JPL, resulting in 1 signal name chosen as net name and (n-1) signal names inconsistent with net name. 404 out of 1085 warnings seem to be of this type.
- Using vim command :%s/_LV_RETURN\; node//n
[x] Some naming inconsistencies for unconnected pins, expected since to be tied to GND. Using vim command :%s/Tom\: GND\; node\: DCB\: None//n, 514 out of 1085 warnings seem to be of this type.

Excluding above, "only" 167 errors left, using vim command :g/_RETURN\; node\|Tom\: GND\; node\: DCB\: None/d.

[x] A few cases of JP_P_LV_SENSE_GND, Tom kept pin number in, e.g. JP0A16_P3_LV_SENSE_GND` We make a rule for this signal that matches his.

ZishuoYang commented 6 years ago

Possible solution to check the 1-to-n nets: use function readnets that puts all nodes of such net in a dict (per net), and check against this dict when signal IDs do not match.

ZishuoYang commented 5 years ago

New rules from @tobannon's latest schematic editing (07 Feb 2019) to be implemented in NetlistGen and/or NetlistCheck:

[Reference: FullBP_Notes_TomO_07Feb2019.pdf]

[x] ALL FRO (never-used) elink inputs must be connected to 1.5V / ground bias connections:
- [x] Confirm that high impedance setting can be accomplished on each individual port rather than as part of a larger bank setting (ie becomes an issue if a bank needs to be set to 100 Ohm because some of the elinks are used, but some are FRO). See https://github.com/umd-lhcb/lab-notes/wiki/Terminate-each-elink-individually
- [x] THE FRO_P and FRO_N associated with EACH DCB slot should be connected to a COMMON 1.5V and ground via 100 Ohm series resistors. The FRO bias 1.5V source must be for the same DCB slot only. The following should be done:
- [x] Change JD#_FRO_DC#_ELK_CH#_P -> JD#_FRO_ELK_P and JD#_FRO_DC#_ELK_CH#_N -> JD#_FRO_ELK_N in JD pin assignments
- [x] What about EC_SEC_CLK_ELK? To verify that these should be input ELKs too. - ZSY
- [x] Check the connections JD#_FRO_ELK_P/N to R(100Ohm) (to JD#_..._1V5/GND not done)
- [x] for the unused EC_SEC_CLK_ELK and MC/EC_DIN_ELKs in each DCB slot, i.e. JD0_FRO_EC_SEC_CLK_ELK_N, JD#_FRO_MC_SEC_DIN_ELK and JD#_FRO_EC_SEC_DIN_ELK: need to treat separately and designate FRO_SEC, i.e. JD0_FRO_SEC_ELK_N.
[x] For each JD, add ADC connections for the ground sense associated with the three most remote hybrid ~power group~s P3, P2_EAST, P1_WEST. Example:
- JD0_FRO_EC_ADC_REF13 … RENAMED AS… JP0A16_P3_LV_SENSE_GND (JD0-D1)
- JD0_FRO_EC_ADC_REF14 … RENAMED AS… JP0J24_P1_WEST_LV_SENSE_GND (JD0-D2)
- JD0_FRO_EC_ADC_REF15 … RENAMED AS… JP0F05_P2_EAST_LV_SENSE_GND (JD0-E1)
- [x] And do not include LV_SENSE_GND in the aux list for identifying the depopulated.
[x] Add remote reset signal line for each DCB master DCB slot:
- [x] Change pin assignments for all JD# H43 to JD#_REMOTE_RESETB. (See PDF above for routing details. Note that the routing to JT connectors will require updating the Telemetry Control Board design for final system.) This is done by updating Signal IDs for all H43s in input/backplane_mapping_DCB.yml, and adding a NetlistGen rule for JD#_REMOTE_RESETB. - ZSY
[x] Check usage of the following ref designators in component naming to address depopulation and part type swaps to facilitate BP inner, middle, and outer variants (see ‘Backplane Variants and DCB Slot Depopulation’ diagram below)
- RB_: Installed for beta (B) variant (and 'B special' aka gamma variant)
- RBSP_: Installed for ‘B special’ (aka gamma aka UTa-plane outer backplane...) variant
- CxRB_: Is capacitor, except for beta variant where a resistor is needed instead.
- i.e. normal is C, depopulated is R.

[x] Because each JD#_1V5 is from two LVR channels (master, slave) that are tied together on both ends, the NetlistGen DCB rule should no longer include _M/_S at the end, i.e. JD0_JPL0_1V5.

yipengsun commented 5 years ago

For EC_ADC_REF13, on the DCB yaml file, no JD connector is specified. How do we know that JD0 should connect to JP0's sense ground?

yipengsun commented 5 years ago

OK, it seems that we should assume JD#_EC_ADC_REFXX should be connected to JP#'s sense ground.

tobannon commented 5 years ago

The following inputs are associated with the unused secondary slow control connections. These are tied to a common bias set separate from the other FRO inputs. The separate components are required to accommodate the 100 terminations already installed on the DCB. Dual parallel 100 ohm resistors are used for each leg to ensure there is at least a 350 to 400 mV differential voltage present. The redundant 100 ohm components are used to simplify the assembly logistics by negating the need to add another component value to the assembly.

So the pin assignments should be updated for each JD such that: JD0_FRO_MC_SEC_DIN_ELK_N --> JD0_FRO_SEC_ELK_N JD0_FRO_MC_SEC_DIN_ELK_P --> JD0_FRO_SEC_ELK_P JD0_FRO_EC_SEC_DIN_ELK_N --> JD0_FRO_SEC_ELK_P JD0_FRO_EC_SEC_DIN_ELK_P --> JD0_FRO_SEC_ELK_N JD0_FRO_EC_SEC_CLK_ELK_N --> JD0_FRO_SEC_ELK_P JD0_FRO_EC_SEC_CLK_ELK_P --> JD0_FRO_SEC_ELK_N

ZishuoYang commented 5 years ago

[x] For now, to keep error-checking going, we have to patch our code and bypass the inconsistent pinout in pigtail SEAM library part, #55.

CoffeeIntoScience commented 5 years ago

For each JD, add ADC connections for the ground sense associated with the three most remote hybrid power groups P3, P2_EAST, P1_WEST.

These are not power groups, these are hybrids. This rule in general seems ambiguous because a DCB is not uniquely associated with a pigtail. Please clarify.

ZishuoYang commented 5 years ago

As described in [Reference: FullBP_Notes_TomO_07Feb2019.pdf] by @tobannon , this is added input to ADC for measuring hybrids that are physically present in all variants (ie P1_WEST, P2_EAST, & P3). He wanted each DCB to associate with a PT, i.e. JD0-JP0 etc. This raises a good point: if JD2-JP2, then on beta JP2 won't have JD2 to connect to.

Discussed with Tom. He accepts the outcome and gave the go-ahead. In addition, we have some redundancy in these measurements, due to the horizontal power groupings. -ZSY

ZishuoYang / UT-Backplane-mapping