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accel-sim / accel-sim-framework

This is the top-level repository for the Accel-Sim framework.
https://accel-sim.github.io
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Observing half Accelsim DRAM bandwidth compare to native #198

Closed expgpgpu closed 1 year ago

expgpgpu commented 1 year ago

Hi, I am running mem_bw workload of GPU_microbenchmark in PTX mode with latest Accelsim code and observing half dram bandwidth with respect to numbers mentioned in Accel-sim ISCA paper.

run command, ./util/job_launching/run_simulations.py -B GPU_Microbenchmark -C QV100-PTX -N myTest-PTX

gpgpusim configuration, QV100-PTX

run logs, Mem BW= 345.807312 (Byte/Clk) Mem BW= 0.000081 (GB/sec) Total Clk number = 582193 gpu_tot_sim_cycle = 588514 gpu_tot_sim_insn = 72515584

In Paper (page-10 TABLE VIII) mentioned mem_bw Hw cycles = 382171 and expecting 16 % Accel-Sim error. But I am observing 52 % Accel-sim error (Total Clk number = 582193). Can you please guide me through if anything missing in observation or to improve dram bandwidth?

yechen3 commented 1 year ago

The clock domain in gpgpusim.config was changed after the paper. You can see the change here

JRPan commented 1 year ago

We are working on that. For now, please use the this config, which should be able to recreate the results in the paper. https://github.com/accel-sim/gpgpu-sim_distribution/blob/a8256e50a6d25338f659da76ff9c3595132f54b2/configs/tested-cfgs/SM7_QV100/gpgpusim.config

Thanks