Testbench required for aes_cip.sv

[skudlur]

Description

Add a testbench for aes_cip.sv to validate it's functionality. Please refer to this for a tutorial on writing a testbench.

Note:

• You are eligible to get brownie points if you report back bugs with the module, add coverage reports, randomized testing and self-assertion tests.

[ninsid711]

can i get assigned

[ninsid711]

also i dont know this stuff so ill take some time

[skudlur]

@SiddharthaRao2005 good luck, assigned

[ninsid711]

im using an online simultator if its fine

[skudlur]

yeah that's fine

On Fri, Oct 13, 2023 at 9:41 PM Siddhartha Aakash Rao < @.***> wrote:

im using an online simultator if its fine

— Reply to this email directly, view it on GitHub https://github.com/acmpesuecc/aes-128-sysverilog-riscv/issues/1#issuecomment-1761766930, or unsubscribe https://github.com/notifications/unsubscribe-auth/AJGTV47TJ53JKIM4PD46LX3X7FR25AVCNFSM6AAAAAA546VSSKVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTONRRG43DMOJTGA . You are receiving this because you authored the thread.Message ID: @.***>

-- Suhas KV

[ninsid711]

its eda playgrounds also which simulator should i use for synopsis its asking a validated account which i dont have

[ninsid711]

[ninsid711]

this is the issue @skudlur

[skudlur]

ahh, iverilog doesn't run systemverilog testbenches. Try running Aldec or Mentor Graphics simulators

On Fri, Oct 13, 2023 at 10:05 PM Siddhartha Aakash Rao < @.***> wrote:

[image: image] https://user-images.githubusercontent.com/139236158/274960488-8805bac5-dd86-4ea8-9cb2-f4a09f93700d.png

— Reply to this email directly, view it on GitHub https://github.com/acmpesuecc/aes-128-sysverilog-riscv/issues/1#issuecomment-1761797265, or unsubscribe https://github.com/notifications/unsubscribe-auth/AJGTV43VGUSC5OBWYMTMXQ3X7FUT5AVCNFSM6AAAAAA546VSSKVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTONRRG44TOMRWGU . You are receiving this because you authored the thread.Message ID: @.***>

-- Suhas KV

[ninsid711]

[ninsid711]

this is what it shows

[ninsid711]

@skudlur

[ninsid711]

is it fine ?

[ninsid711]

@skudlur could you tell me again what was i supposed to do again

[ssether04]

can i get assigned if this is still open?

[ninsid711]

its already been assigned

[ninsid711]

this is what i see now @skudlur

[skudlur]

you need to add the round.sv and roundlast.sv files in the right side of EDA playground. Add the files and try running it again

On Fri, Oct 13, 2023 at 11:11 PM Siddhartha Aakash Rao < @.***> wrote:

[image: image] https://user-images.githubusercontent.com/139236158/274989228-33a0e3a4-3996-456b-b467-7c4889757397.png this is what i see now @skudlur https://github.com/skudlur

— Reply to this email directly, view it on GitHub https://github.com/acmpesuecc/aes-128-sysverilog-riscv/issues/1#issuecomment-1761918475, or unsubscribe https://github.com/notifications/unsubscribe-auth/AJGTV45MJ2XE4Y4XBV6CSCTX7F4NFAVCNFSM6AAAAAA546VSSKVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTONRRHEYTQNBXGU . You are receiving this because you were mentioned.Message ID: @.***>

-- Suhas KV

[ninsid711]

like this ?

[ninsid711]

@skudlur DOES THIS WORK !!!!?????