aignacio / ravenoc

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
MIT License
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Why the project only has axi slave interface #6

Closed Elena32061 closed 2 years ago

Elena32061 commented 2 years ago

Why does the network interface only need the axi slave interface? Is it because you only consider connecting to the CPU? If the situation is that the CPUs not only need to actively initiate writes ,but also need to be read. Should I consider add an axi master interface?

aignacio commented 2 years ago

Hey @Elena32061,

this NoC considers the NI as a passive slave agent, which means that if you want to either send or receive packets through the NoC you have to provide the data from a CPU or a DMA, that's why we have buffers in each virtual channel to accommodate a programmable set of flits. If you want the NoC to be capable to write standalone without any master in the bus, you can wrap the NI with an AXI Master lets say that as soon as it receives a packet, it writes it through the bus, the only issue is that this master needs to understand the header flit to know how big needs to be the size of the burst.