Documentation for axil_interconnect

[catkira]

I am using axil_interconnect with this configuration (ADDRESS_WIDTH = 16)

axil_interconnect_wrap_1x4 #(
    .DATA_WIDTH(32),
    .ADDR_WIDTH(ADDRESS_WIDTH),
    .M_REGIONS(1),
    .M00_ADDR_WIDTH(ADDRESS_WIDTH),
    .M01_ADDR_WIDTH(ADDRESS_WIDTH),
    .M02_ADDR_WIDTH(ADDRESS_WIDTH),
    .M03_ADDR_WIDTH(ADDRESS_WIDTH),
    .M00_BASE_ADDR(16'h1000),
    .M01_BASE_ADDR(16'h2000),
    .M02_BASE_ADDR(16'h3000),
    .M03_BASE_ADDR(16'h4000)
)

I am getting this error

INFO cocotb: Region not aligned:
INFO cocotb:  0 ( 0): 1000 / 16 -- 0000-ffff

Is there somewhere a documentation how the parameters of this core work?

[catkira]

ok I got it to work like this, but I still think a bit documentation would be good :)

localparam ADDRESS_WIDTH = 16;
localparam OFFSET_ADDR_WIDTH = ADDRESS_WIDTH - 2;
axil_interconnect_wrap_1x4 #(
    .DATA_WIDTH(32),
    .ADDR_WIDTH(ADDRESS_WIDTH),
    .M_REGIONS(1),
    .M00_ADDR_WIDTH(OFFSET_ADDR_WIDTH),
    .M01_ADDR_WIDTH(OFFSET_ADDR_WIDTH),
    .M02_ADDR_WIDTH(OFFSET_ADDR_WIDTH),
    .M03_ADDR_WIDTH(OFFSET_ADDR_WIDTH),
    .M00_BASE_ADDR(0 << OFFSET_ADDR_WIDTH),
    .M01_BASE_ADDR(1 << OFFSET_ADDR_WIDTH),
    .M02_BASE_ADDR(2 << OFFSET_ADDR_WIDTH),
    .M03_BASE_ADDR(3 << OFFSET_ADDR_WIDTH)
)

[catkira]

I still have one question, I currently get a WIDTH warning here

.m00_axil_awaddr(s_axi_fifo_awaddr),

because m00_axil_awaddr is 16 bit wide, but I made my s_axi_fifo_awaddr only 14 bit wide. Does it make sense that the connected slaves also see the base address? I thought no, so I removed the base address from the slave addresses.

[alexforencich]

Depends. First, there is no easy way to make each address port a different width, so making them all full width is really the only option when you're not using the generated wrapper. Second, if M_REGIONS is set to anything other than 1, you may need some of the MSBs to identify the region. But yes, in most cases, you'll truncate off the MSBs at some point between the interconnect module and downstream components.

Also, all of the interconnect/crossbar modules have an "auto addressing" mode where when you tie off all of the BASE_ADDR parameters to 0, it will compute all of the base addresses automatically based on the ADDR_WIDTH parameters.