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alexforencich / verilog-axi

Verilog AXI components for FPGA implementation
MIT License
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AXI interconnect #51

Open ilamparithy01 opened 1 year ago

ilamparithy01 commented 1 year ago

Hi , I like to use AXI interconnect , I am going to connect 3 slave device to the master IO of interconnect , I want to have different base address , How to det different base address.

alexforencich commented 1 year ago

Set ADDR_WIDTH and BASE_ADDR appropriately. There are some details here: https://github.com/alexforencich/verilog-axi/issues/16

ilamparithy01 commented 1 year ago

Hi Alexforencich , Thanks for the information , I am connecting single master and 3 to 4 slave , let me test and come back to you.