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alexforencich / verilog-cam

Verilog Content Addressable Memory Module
MIT License
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How to use the cam module? #1

Open Jzone315 opened 6 years ago

Jzone315 commented 6 years ago

Hi: Sorry to bother you again. This time i am using the cam module , but i found some of the ports are being unspecified, so i want to know is there any timing specifying of the ports of cam.v, for example what did the ports write_enable and write_delete mean? Thanks a lot for your help.

Jzone315 commented 6 years ago

In addition, what is the parameter SLICE_WIDTH mean? i had no idea of how it works.

alexforencich commented 6 years ago

So what the CAM module does is split the data bus into slices, with each slice corresponding to an SRL16, SRL32, or block RAM. SLICE_WIDTH determines how wide the slices are. If you want SRL16, set it to 4. If you want SRL32, set it to 5. If you want to use 512x32 BRAMs, set it to 9. What you select will depend on what resources your target device has, the required size of the CAM, etc. In principle, you can set this value to whatever you want and the CAM will work, it just might consume a lot more logic resources.

write_enable works just like any other synchronous RAM - set it high with the other write signals to initiate a write operation. write_delete asserted together with write_enable causes the entry at write_addr to be removed from the CAM. Also, these control signals are ignored while write_busy is high, indicating that the CAM is performing an internal operation.

Jzone315 commented 6 years ago

Thanks a lot, your answer has solved many of my questions, i am using the CAM module in both xilinx kintex and kintex ultrascale platform, with CAM_STYLE chose "BRAM" mode, i had did the verification, 9 seemed to be the best parameter for both, thanks again, i had learned a lot.