I'm trying to get better at verilog and i saw the project coding style and i get a little confused.
The FSMs are in the Mealy method but outputs updated according to clock. why to do so? why not to use the Moore method?
for example in the _ip_eth_rx.v_:
Here been created 2 registers: _m_ip_hdr_validreg, _m_ip_hdr_validnext.
there is combinational always block that determines the value of _m_ip_hdr_validnext and there is clocked always block that assign _m_ip_hdr_validnext to _m_ip_hdr_valid_reg_:
And in the end there is an assign of _m_ip_hdr_validreg to the output _m_ip_hdrvalid:
Why to do this? why not to use one clocked always block and there you will control the FSM and the outputs? either way the outputs are clocked out.
I ask this only for self improvement and to get better understanding.
I'm trying to get better at verilog and i saw the project coding style and i get a little confused. The FSMs are in the Mealy method but outputs updated according to clock. why to do so? why not to use the Moore method? for example in the _ip_eth_rx.v_:
Here been created 2 registers: _m_ip_hdr_validreg, _m_ip_hdr_validnext. there is combinational always block that determines the value of _m_ip_hdr_validnext and there is clocked always block that assign _m_ip_hdr_validnext to _m_ip_hdr_valid_reg_:
And in the end there is an assign of _m_ip_hdr_validreg to the output _m_ip_hdrvalid:
Why to do this? why not to use one clocked always block and there you will control the FSM and the outputs? either way the outputs are clocked out.
I ask this only for self improvement and to get better understanding.