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alexforencich / verilog-ethernet

Verilog Ethernet components for FPGA implementation
MIT License
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Bug in ssio_sdr_in_diff.v #182

Open AlexLao512 opened 11 months ago

AlexLao512 commented 11 months ago

I found a small bug in ssio_sdr_in_diff.v

I don't know if you prefer a PR or an issue for small bug fixes. 

diff --git a/rtl/ssio_sdr_in_diff.v b/rtl/ssio_sdr_in_diff.v
index 7a0d7c1..fd05326 100644
--- a/rtl/ssio_sdr_in_diff.v
+++ b/rtl/ssio_sdr_in_diff.v
@@ -101,11 +101,10 @@ endgenerate

 ssio_sdr_in #(
     .TARGET(TARGET),
-    .IODDR_STYLE(IODDR_STYLE),
     .CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
     .WIDTH(WIDTH)
 )
-ssio_ddr_in_inst(
+ssio_sdr_in_inst(
     .input_clk(input_clk),
     .input_d(input_d),
     .output_clk(output_clk),