I made modifications directly from the ExaNIC_X10 project, only modifying the pin constraints and ref_clk constraints. I found that the project also couldn't run ，and phy was not connected.
I can directly use the 10G/25G ETH subsystem of Xilinx ， see that phy can be connected. Attached is the project I modified. Can you give me some suggestions. vivado version：2019.1
ExaNIC_X10_ku060.zip
I made modifications directly from the ExaNIC_X10 project, only modifying the pin constraints and ref_clk constraints. I found that the project also couldn't run ，and phy was not connected. I can directly use the 10G/25G ETH subsystem of Xilinx ， see that phy can be connected. Attached is the project I modified. Can you give me some suggestions. vivado version：2019.1 ExaNIC_X10_ku060.zip