search

aloebs29 / flash_management

Flash management stack for the STM32L432KC MCU and MT29F1G01ABAFDWB SPI NAND flash chip.
MIT License
29 stars 16 forks source link

Is multi-planar nand not supported? #5

Closed EitanTal closed 2 months ago

EitanTal commented 2 months ago

When looking at the datahseet for MT29F1G01AAADD, it shows the nand is split into 2 planes. I was unable to retrieve the datasheet for this device (MT29F1G01ABAFDWB), but I imagine it is similar.

being multi-planar, it has these consequences:

  1. When you access the cache register, you have to specify the LSB of block number (repeated from previous page-load command), as address bit no. 12, in front of the existing [11...0] column bits
  2. page-copy from one plane to the other is not supported (Known as Internal Data Move in the datasheet)

I see no evidence for either of these by looking at spi_nand.c

aloebs29 commented 2 months ago

You are correct that I did not implement support for multi-planar NAND devices -- the device I used just had a single plane (the chip is likely discontinued at this point, which is probably why a datasheet is hard to find).

I believe your understanding of the changes that are needed to support a multi-planar NAND device is also correct. This comment (and the linked repo) should be a good starting point/reference.

EitanTal commented 2 months ago

That repo works. May be worth-while to mention it in the readme.md