Closed AditiDarade closed 1 year ago
riscv_alu.v - ALU is just a RISCV ALU,
CSR - control / status register
Core - controls the whole thing
csr_regfile - is more directly related to the csr unit that we can see in the RISCV pipeline
riscv_decode.v - Uses RISCV decoder from decoder.v to decode a fetched instruction.
riscv_decoder.v - Defines decoding rules
riscv_defs.v - Gives human readable names to signal values
riscv_divider.v - Defines a division unit as part of the RISCV m extension
riscv_exec.v - Appears to handle ALU operations and outputs as well as branch handling and program counter increasing
riscv_fetch.v - fetch
riscv_issue.v - Privilege level, issue(?), pipeline status tracking (Blocking and staling, scoreboard), loadstore unit, CSR unit, multiplication (M extension, checker interface(?))
riscv_lsu.v - Load store unit
riscv_mmu.v - Memory management unit, uses the load store unit.
riscv_multiplier.v - Defines a multiplication unit as part of the RISCV M extension
riscv_pipe_ctrl.v - Handles the pipeline, works with the issue file, handles rightback/commit
riscv_regfile.v - Defines registers as well as methods on them
riscv_trace_sim.v - File for simulation the core and software, assigning names to registers and signals
riscv_xilinx_2r1w.v ?
riscv_alu.v - ALU is just a RISCV ALU,
CSR - control / status register
Core - controls the whole thing
csr_regfile - is more directly related to the csr unit that we can see in the RISCV pipeline
riscv_decode.v - Uses RISCV decoder from decoder.v to decode a fetched instruction.
riscv_decoder.v - Defines decoding rules
riscv_defs.v - Gives human readable names to signal values
riscv_divider.v - Defines a division unit as part of the RISCV m extension
riscv_exec.v - Appears to handle ALU operations and outputs as well as branch handling and program counter increasing
riscv_fetch.v - fetch
riscv_issue.v - Privilege level, issue(?), pipeline status tracking (Blocking and staling, scoreboard), loadstore unit, CSR unit, multiplication (M extension, checker interface(?))
riscv_lsu.v - Load store unit
riscv_mmu.v - Memory management unit, uses the load store unit.
riscv_multiplier.v - Defines a multiplication unit as part of the RISCV M extension
riscv_pipe_ctrl.v - Handles the pipeline, works with the issue file, handles rightback/commit
riscv_regfile.v - Defines registers as well as methods on them
riscv_trace_sim.v - File for simulation the core and software, assigning names to registers and signals
riscv_xilinx_2r1w.v ?