azonenberg openfpga issues

azonenberg / openfpga

Open FPGA tools

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issues

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Allow Windows builds using MSYS2 Environment

#41 cr1901 closed 8 years ago
0
Timing-driven placement

#40 azonenberg opened 8 years ago
0
Implement post-PAR timing analysis

#39 azonenberg opened 8 years ago
1
Support supplying gp4par options --unused-drive, --unused-pull via toplevel module attributes

#38 whitequark closed 7 years ago
1
Figure out constraint file or other way to support LOC constraints on vector top-level ports

#37 azonenberg closed 7 years ago
1
Support for PDELAY/edge detector block in edge detector mode

#36 azonenberg closed 8 years ago
1
Support for SPI slave block

#35 azonenberg opened 8 years ago
0
Support for DCMP/PWM block

#34 azonenberg opened 8 years ago
0
Support for PGEN mode of LUT4/PGEN block

#33 azonenberg closed 8 years ago
0
Support for DAC

#32 azonenberg closed 7 years ago
0
Support for ADC

#31 azonenberg opened 8 years ago
0
Techmapping: merge GP_DFF + GP_INV to GP_DFF with output inverter

#30 azonenberg closed 7 years ago
1
Support for latch mode of GP_DFF cells (separate primitive GP_DLATCH?)

#29 azonenberg closed 7 years ago
0
Support for output inverter on GP_DFF cells

#28 azonenberg closed 8 years ago
0
Create framework for co-simulation test cases that compare hardware-in-loop behavior to iverilog simulation

#27 azonenberg opened 8 years ago
0
Synchronize defaults with Yosys models

#26 whitequark closed 8 years ago
0
Create framework for multiple hard IP blocks sharing one set of config bits

#25 azonenberg closed 8 years ago
0
Allow GP_DFF cells to be placed in unused GP_SHREG sites

#24 azonenberg opened 8 years ago
0
PAR should always exit with the best solution found to date, rather than the current placement when the optimizer gave up

#23 azonenberg closed 7 years ago
0
Add Verilog-AMS sim models for analog hard IP

#22 azonenberg opened 8 years ago
0
GP_RCOSC.OSC_FREQ does not work

#21 whitequark closed 8 years ago
1
Allow placing GP_INV in GP_LUT sites

#20 whitequark closed 8 years ago
0
ERROR: Cell ...$314 has invalid LOC constraint P7 (site is of type GP_IOBUF, instance is of type GP_2LUT)

#19 whitequark closed 8 years ago
4
ERROR: Net number in module should be of type integer but isn't

#18 whitequark closed 8 years ago
1
Logic loop cannot be synthesized

#17 whitequark closed 8 years ago
0
Uninitialized read

#16 whitequark closed 8 years ago
1
Use a RNG independent of machine, OS, endianness, etc

#15 whitequark closed 7 years ago
2
Check constraint values more stringently

#14 whitequark closed 8 years ago
0
GP_SHREG PAR bug

#13 whitequark closed 8 years ago
0
Various improvements

#12 whitequark closed 8 years ago
0
$assert cells should be ignored during synthesis

#11 whitequark closed 8 years ago
1
ERROR: Cell "$abc$..." is of type "$_NOT_" which is not a valid GreenPak4 primitive

#10 whitequark closed 8 years ago
6
INTERNAL ERROR: tried to assign node to illegal site

#9 whitequark closed 8 years ago
2
Support for Yosys' -q/-l/-L options

#8 whitequark closed 8 years ago
1
Module-related bug

#7 whitequark closed 8 years ago
1
More sensible naming for RCOSC

#6 whitequark closed 8 years ago
0
Disallow omission of primitive parameters

#5 whitequark closed 8 years ago
1
Various improvements

#4 whitequark closed 8 years ago
0
Make tables in documentation less busy

#3 whitequark closed 8 years ago
0
Reformat documentation

#2 whitequark closed 8 years ago
0
C++11 required for build

#1 cliffordwolf closed 8 years ago
1