Open rongcuid opened 2 years ago
Neither cadence nor Synopsys tools are required for Verilator, so you can comment out the offending checks
You may also be able to set IGNORE_CADENV=1
.
For example, make machine IGNORE_CADENV=1
.
Not really working (under machines/
):
$ BSG_PLATFORM=verilator IGNORE_CADENV=1 make
Makefile.vcs:6: VCS must be set; probably need VCS_HOME, SNPSLMD_LICENSE_FILE too, maybe LM_LICENSE file
Makefile.vcs:3: /home/rongcuid/src/bsg/bsg_manycore/../bsg_cadenv/cadenv.mk: No such file or directory
make: *** No rule to make target '/home/rongcuid/src/bsg/bsg_manycore/../bsg_cadenv/cadenv.mk'. Stop.
I didn't edit the Makefiles, though.
I tried commenting out the include in makefile, but I cannot get make machine
to work. I get a huge scroll of warnings and errors, mostly something like thisL
%Error-TIMESCALEMOD: /home/rongcuid/src/bsg/basejump_stl/bsg_noc/bsg_noc_pkg.v:5:9: Timescale missing on this module as
other modules have it (IEEE 1800-2017 3.14.2.2)
Are you using the Verilator included or your own version? There is a “no timescale” parameter to add, but I’m not sure why the issue would be popping up in your build and not ours
I have verilator 4.038 installed on my machine, so I think this is the one used. I don't see verilator installed by BSG tools, though.
Oh yeah that's fairly old. We've tagged 4.220 as a golden release for bsg_manycore. In general, would recommend you start with the bladerunner meta-repo at: https://github.com/bespoke-silicon-group/bsg_bladerunner, but at the least I would try upgrading Verilator
I was not aware of the repo. I will try updating verilator first. Perhaps you can update the README and website for it?
I had #649 applied so I will need to figure out what to do first, though.
As title. I am unable to do
make machine
even with the variable set. It looks like BSG is still expecting the Cadence tools. Are they required?