In this PR we address JTAG-based ADIv6 support, as we didn't have an example of a JTAG target for this when doing the initial support, but one has turned up via a user, allowing the ADIv6 support to be sorted out and completed.
This has seen a couple of challenges to get it to a usable state - the first of which is that the JTAG ACK values change between ADIv5 and ADIv6, with the latter splitting the OK and FAULT ACKs into different values (yay!). This means that the JTAG low-level code for ADI now has version-dependant behaviour, requiring a new remote protocol packet to properly handle.
The second challenge is that the JTAG IDCode version bits now have additional valid values, which it turns out come from the CoreSight SoC TRMs, that determine if the TAP is for a JTAG-DPv0 or a JTAG-DPv1. The new JTAG-DP implements the DPIDR field but the DP registers do not reset with the state machine, so requiring some initial setup to ensure we read the right thing to determine ID. This also comes with needing to deal with devices that implement the Dormant State part of the JTAG <-> SWD switch-over state machine.
This PR includes the changes needed to correctly identify the Cortex-M55 debug components and some more of the CoreSight SoC-600(M) debug components and allow debugging Cortex-M55 processors.
Detailed description
In this PR we address JTAG-based ADIv6 support, as we didn't have an example of a JTAG target for this when doing the initial support, but one has turned up via a user, allowing the ADIv6 support to be sorted out and completed.
This has seen a couple of challenges to get it to a usable state - the first of which is that the JTAG ACK values change between ADIv5 and ADIv6, with the latter splitting the OK and FAULT ACKs into different values (yay!). This means that the JTAG low-level code for ADI now has version-dependant behaviour, requiring a new remote protocol packet to properly handle.
The second challenge is that the JTAG IDCode version bits now have additional valid values, which it turns out come from the CoreSight SoC TRMs, that determine if the TAP is for a JTAG-DPv0 or a JTAG-DPv1. The new JTAG-DP implements the DPIDR field but the DP registers do not reset with the state machine, so requiring some initial setup to ensure we read the right thing to determine ID. This also comes with needing to deal with devices that implement the Dormant State part of the JTAG <-> SWD switch-over state machine.
This PR includes the changes needed to correctly identify the Cortex-M55 debug components and some more of the CoreSight SoC-600(M) debug components and allow debugging Cortex-M55 processors.
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Closing issues
Fixes #1970