This fixes a clock domain crossing bug when mkDualClockBramFIFOF is wider than 36 bits wide.
This is needed because when crossing a clock domain in multiple sync FIFOs, responses may not be available in the same clock cycle.
When I made this change, it fixed bugs in two different designs that used ddr3 on vc707. One was a heavily modified version of the ddr_minimal test, and the other was the inorder pipelined RISC-V processor.
This fixes a clock domain crossing bug when mkDualClockBramFIFOF is wider than 36 bits wide.
This is needed because when crossing a clock domain in multiple sync FIFOs, responses may not be available in the same clock cycle.
When I made this change, it fixed bugs in two different designs that used ddr3 on vc707. One was a heavily modified version of the ddr_minimal test, and the other was the inorder pipelined RISC-V processor.