Generate Verilog / VHDL code for fixpoint filters using jinja templates

[chipmuenk]

This is not to replace Amaranth HDL generation but rather to complement it, e.g. for easy reverse engineering and parametrization of legacy Verilog / VHDL code

https://www.ericmacedo.com/generating-code-from-templates-using-python-and-jinja2.html