Unsigned number are padded to the left with ones instead of zeros

[RustamC]

While testing synlig, I encountered a problem with a simple counter: https://github.com/chipsalliance/synlig/issues/2624 .

In this code:

module counter (  input clk, input rstn, output reg[3:0] out);
  always @ (posedge clk) begin
    if (! rstn)
      out <= 0;
    else
      out <= out + 4'h1;
  end
endmodule

integer literal 'h1 is expanded to 4'b1111 instead of 4'b0001 causing wrong synthesis.

At the same time, if one specifies an optional size constant ('h1 -> 4'h1), integer literal will be expanded as expected to 4'b0001.