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chipsalliance / UHDM-integration-tests

Apache License 2.0
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Add test for signed wire #701

Closed mandrys closed 1 year ago

mandrys commented 1 year ago

Test provided for plugin changes in https://github.com/chipsalliance/yosys-f4pga-plugins/pull/435. A workflow with the test included: https://github.com/antmicro/yosys-systemverilog/pull/1273.

mglb commented 1 year ago

This test doesn't really test that fix. It passes on master: https://github.com/antmicro/yosys-systemverilog/actions/runs/3894891200

BTW. let's use one naming convention. Since most tests use "CamelCase", it would be nice to name it "SignedWire".

mandrys commented 1 year ago

Renamed the test according to the naming convention.