chipsalliance / fpga-interchange-tests

Repository to run extensive tests on the FPGA interchange format
https://chipsalliance.github.io/fpga-interchange-tests
ISC License
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A Tcl script that can take an arbitrary netlist and use Vivado to create pin placements #121

Open clavin-xlnx opened 2 years ago

clavin-xlnx commented 2 years ago

A useful Tcl script would be to use Vivado to generate a high quality I/O pin placement from a synthesized netlist. This would be a one-time upfront run. The input would be a synthesized netlist (such as EDIF, or similar) and output would be an XDC file with port placements assigned as constraints.