Feature tests for Ultrascale+

chipsalliance / fpga-interchange-tests

Repository to run extensive tests on the FPGA interchange format

https://chipsalliance.github.io/fpga-interchange-tests

ISC License

8 stars 9 forks source link

Feature tests for Ultrascale+ #93

Closed kboronski-ant closed 2 years ago

kboronski-ant commented 2 years ago

This PR adds the following PASSING tests for Ultrascale+ family (ZCU104):

DRAM (with differential clock input):

1_32x1s
1_32m
1_32m16
1_64m
1_64m8
1_64x8sw
1_128x1s
1_128x1d
1_256x1s
1_256x1d
1_512x1s
2_32x1d
2_64x1d
2_128x1s
4_32x1s
4_32x2s
4_64x1s
8_32x1s

SING-IO:

OBUFT
IOBUF

LUT:

DIFF_IO:

IBUFDS
OBUFDS

Block RAM:

RAMB18E2 (ram, ram_36bit)
RAMB36E2 (ram_72bit)

MMCM:

MMCME4_ADV

acomodi commented 2 years ago

@kboronski-ant There is a conflict with the RapidWright bump, once solved we can start the CI checks

acomodi commented 2 years ago

I see that the failing tests are causing CI to go red, we can either set them with a failure allowed flag, or wait to add them and remove them from this PR:

11:55:34 | Tests not allowed to fail:
11:55:34 |  xcup oserdese3
11:55:34 |  xcup iobufds
11:55:34 |  xcup obuft
11:55:34 |  xcup obuftds
11:55:34 |  xcup iobuf
11:55:34 |  xcup ram_36bit_diff

On a side note, there is a failure in the licensing checking which causes https://github.com/SymbiFlow/fpga-interchange-tests/runs/5317995647?check_suite_focus=true to go red

GitHub
Feature tests for Ultrascale+ · SymbiFlow/fpga-interchange-tests@21f0cfd
Repository to run extensive tests on the FPGA interchange format - Feature tests for Ultrascale+ · SymbiFlow/fpga-interchange-tests@21f0cfd

kboronski-ant commented 2 years ago

I added PLL tests and allowed failures.

Also, just made sure that sing-io and diff-io designs that fail do synthesize in Vivado, everything else was tested earlier.

acomodi commented 2 years ago

On a second thought it would be better to just remove the failing tests and organize them in "failing classes" so that we can more easily address them and understand the underlying issue.

kboronski-ant commented 2 years ago

@acomodi I don't have any special license and I had no trouble generating bitstreams targetted for XCZU7EV. I don't know why the bitstreams got disabled.

kboronski-ant commented 2 years ago

~Blocked by #110~

acomodi commented 2 years ago

@kboronski-ant There are still some pending comments, after those are solved I think we can go ahead and merge