Testarch with timing - Githubissues

chipsalliance / python-fpga-interchange

Python interface to FPGA interchange format

ISC License

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Testarch with timing #102

Closed mtdudek closed 3 years ago

mtdudek commented 3 years ago

This PR contains python script for static timing analysis of physical netlists. It uses modified fpga_interchange schema with modification in pinDelay struck. I've change BELPinIdx to StringIdx.

It's still WIP