chip_info: Don't require 0,0 tile type to be exactly NULL

chipsalliance / python-fpga-interchange

Python interface to FPGA interchange format

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chip_info: Don't require 0,0 tile type to be exactly NULL #104

Closed gatecat closed 3 years ago

gatecat commented 3 years ago

The check that there are no wires in this tile (other than dummy wires) is more relevant in any case, so there's no need any more to so strict about the name of the tile type.

This is needed for UltraScale+ support, where the 0,0 tile is HPIO_TERM_L_DA6_TERM_T_FT but still empty.