chipsalliance / python-fpga-interchange

Python interface to FPGA interchange format
ISC License
41 stars 12 forks source link

UltraScale+ device config #105

Closed gatecat closed 3 years ago

gatecat commented 3 years ago

This currently gets as far as creating a chipdb (although a RapidWright with verification patched out is needed due to https://github.com/Xilinx/RapidWright/issues/194). nextpnr is currently hitting an assertion failure when using the chipdb which I'm investigating.