Automatic top module detection

chipsalliance / python-fpga-interchange

Python interface to FPGA interchange format

ISC License

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Automatic top module detection #158

Closed mkurc-ant closed 2 years ago

mkurc-ant commented 2 years ago

This PR adds automatic top-level module detection when converting from Yosys JSON to logical netlist. The top-level module name can still be manually specified via the --top argument.