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chipsalliance / python-fpga-interchange

Python interface to FPGA interchange format
ISC License
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Add macro content to chipdb #68

Closed gatecat closed 3 years ago

gatecat commented 3 years ago

Depends on SymbiFlow/fpga-interchange-schema#42

This only contains the macro content currently, it is not outputting the exception and parameter mapping rules yet.

gatecat commented 3 years ago

A question I have is how to provide the macro to cell mapping as well as the mapping rules to the device database, at least for Xilinx devices. I suppose we can leverage the patching mechanism as it happens for the Luts definitions as well as for the constraints, right?

Yes, initially we will probably have to use the patching mechanism. For the longer term, hopefully RapidWright might be able to provide this info too, I've created Xilinx/RapidWright#162 for this.

gatecat commented 3 years ago

SymbiFlow/fpga-interchange-schema#42 has been merged now, so hopefully this is ready as well (will need a release cut once merged as its a chipdb change).

gatecat commented 3 years ago

Yea, looks like that got cherrypicked into this. Thanks!