chipsalliance / python-fpga-interchange

Python interface to FPGA interchange format
ISC License
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Assert that (0, 0) really is empty #87

Closed gatecat closed 3 years ago

gatecat commented 3 years ago

This improves the contract checking for #34, which does need to be fixed properly at some point, but at least makes a breach of this contract result in a Python assertion failure rather than a nextpnr segfault (leading to the fun debugging https://github.com/gatecat/prjoxide/commit/e62452795d6ec8a4d0207df88b8d49d0bed0207e)