populate chip info: fix assertion

chipsalliance / python-fpga-interchange

Python interface to FPGA interchange format

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populate chip info: fix assertion #88

Closed acomodi closed 3 years ago

acomodi commented 3 years ago

It appears that, for xilinx devices, the (0, 0) tile contains one wire named DUMMYFOO. This PR fixes the assertion to not fail if all wires in the null_tile_type are dummy in reality.

This PR also syncs the setup version with the current tag.

acomodi commented 3 years ago

at least for now

Agreed, these checks do feel a bit fragile at the moment. As soon as more archs get added, we need to revisit this. For the moment I have added a FIXME comment