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chipsalliance / python-fpga-interchange

Python interface to FPGA interchange format
ISC License
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Add interchange clustering definition #91

Closed acomodi closed 3 years ago

acomodi commented 3 years ago

This PR is based on https://github.com/SymbiFlow/python-fpga-interchange/pull/70 and aims at redefining the BEL chaining to make it more flexible and allow also the definition of clusters to guide nextpnr placement.

It mainly detaches from using the schema, and directly adds information to the nextpnr chipdb.

It still is marked as WIP as it needs more iterations to get to a stable and reviewable state.

acomodi commented 3 years ago

I have refactored the whole clustering for the interchange a bit, so as to have a more concise and possibly cleaner description.

Now, with the changes combined in nextpnr, we can still place and route carry chains for the counter test correctly, and I am currently testing the Murax design implementation.

With these modifications, it should be more trivial to add also LUT+FF cluster definitions (which will not have the chainable_ports as carry chains do).

The idea is to have a set of cell and the corresponding pins for a root cluster type, so that, during placement, the BELs to use for the cluster cells connected to the root can be discovered dynamically through a quick expansion.