chipsalliance python-fpga-interchange issues

chipsalliance / python-fpga-interchange

Python interface to FPGA interchange format

ISC License

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issues

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Cleaner nextpnr BBA generation

#66 gatecat opened 3 years ago
2
Add default cell connections to chipdb

#65 gatecat closed 3 years ago
2
device_resources: Adding more site type fields

#64 gatecat closed 3 years ago
0
fasm: add init file to correctly package the fasm_generators dir

#63 acomodi closed 3 years ago
0
fasm: explicit fasm file argument

#62 acomodi closed 3 years ago
0
Invalid DCP when the BUFG route-thru is used

#61 acomodi opened 3 years ago
0
Enable disabling of route-thru PIPs for BUFGCTRL

#60 gatecat closed 3 years ago
0
Replace local license checks with the SymbiFlow/actions/checks@main action

#59 mithro opened 3 years ago
1
fpga_interchange: allow 'x' and 'z' special values

#58 kowalewskijan closed 3 years ago
2
Initial FASM generator

#57 acomodi closed 3 years ago
20
chip_info: Bounds check LUT indices

#56 gatecat closed 3 years ago
1
yosys_json: Leave cHex and cBinary parameters alone

#55 gatecat closed 3 years ago
0
interchange_capnp: fix enum assignment when reading phys netlist

#54 acomodi closed 3 years ago
0
nexus: Update device_config.yaml

#53 gatecat closed 3 years ago
1
Prepare for v0.0.8 release cut.

#52 litghost closed 3 years ago
0
Add some top level comments to logical_netlist and physical_netlist.

#51 litghost closed 3 years ago
0
Add entry points for command line tools.

#50 litghost closed 3 years ago
2
Have add_prim_lib use DeviceResources.strList when patching.

#49 litghost closed 3 years ago
0
Add LUT output pins to chipdb.

#48 litghost closed 3 years ago
0
add_prim_lib should use indexed strings from DeviceResources instead of nested LogicalNetlist

#47 gatecat closed 3 years ago
2
Set default parameters on logical netlists from Yosys JSON.

#46 litghost closed 3 years ago
0
Add tool for importing primLibs from Yosys JSON

#45 gatecat closed 3 years ago
7
tech-doc-update

#44 vmskhan closed 3 years ago
0
nexus: Add stub device_config.yaml

#43 gatecat closed 3 years ago
1
grammatical update

#42 vmskhan closed 3 years ago
0
Update requirements path.

#41 litghost closed 3 years ago
0
Add support for listing global buffer BELs.

#40 litghost closed 3 years ago
0
Increment version in setup.py

#39 litghost closed 3 years ago
0
Add local site inverter data, along with some constant network meta.

#38 litghost closed 3 years ago
0
Convert Yosys binary strings to the format specified from the device database.

#37 litghost closed 3 years ago
0
Actually increment version.

#36 litghost closed 3 years ago
0
Setup automatic publishing packages to PyPI

#35 mithro opened 3 years ago
2
Requiring a NULL tile at (0, 0) is Xilinx-specific

#34 gatecat opened 3 years ago
5
Fix case of a tile without any wires

#33 gatecat closed 3 years ago
0
Add pseudo pip data and fix some parameter pins.

#32 litghost closed 3 years ago
0
Optimize node and pip walking

#31 litghost opened 3 years ago
0
Improve YAML anchor names

#30 litghost opened 3 years ago
0
Add XML support to plaintext FPGA interchange

#29 litghost opened 3 years ago
0
Need to create integrated FPGA interchange CI

#28 litghost closed 3 years ago
8
Need a FPGA interchange to FASM generator

#27 litghost closed 3 years ago
5
Add LUT element information to enable simple LUT rotation.

#26 litghost closed 3 years ago
0
Use constant fields to remove hard-coded constants.

#25 litghost closed 3 years ago
1
Update schema path now that schema has it's own repository.

#24 litghost closed 3 years ago
1
Add constant network to FPGA interchange BBA

#23 litghost closed 3 years ago
0
Prune unused cells from output logical netlist.

#22 litghost closed 3 years ago
0
FPGA interchange logical netlist GND/VCC cell references should come from device database

#21 litghost closed 3 years ago
1
Add converter from Yosys JSON to FPGA interchange logical netlist.

#20 litghost closed 3 years ago
0
Problems with rapidyaml requirement

#19 ajelinski closed 3 years ago
2
Finish nextpnr BBA emission to the point where it can route a wire

#18 litghost closed 3 years ago
0
Add nextpnr BBA emission makefile

#17 litghost closed 3 years ago
0

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