chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
Apache License 2.0
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For riscv vector extension, is mask/tail agnostic with wirte-1s supported? #907

Closed jlong299 closed 1 year ago

jlong299 commented 2 years ago

For riscv vector extension, is mask/tail agnostic with wirte-1s supported? In other word, if there are two implementations of DUT with old-value and wirte-1s policies respectively for ma/ta, will they get the same final result with input generated by riscv-dv? Thanks.