chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
Apache License 2.0
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Is the coverage model I generated broken when I run ‘cov' command? #918

Open Zhengshuhang opened 1 year ago

Zhengshuhang commented 1 year ago

Hi, I am a new learner in ibex DV,I successfully run the run in CentOS7.9,VCS2020.03,spike; but when I run the following command: cov --dir out_2022-11-30/spike_sim

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I find no error ,following is the compile.log and sim_riscv_instr_cov_test_0_0.log: compile.log sim_riscv_instr_cov_test_0_0.log However,when I try to open the test.vdb, it seems to be corrupted:

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Can someone help me?