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chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
Apache License 2.0
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SEW=16 vfcvt/vfwcvt instruction #933

Closed chLZX closed 1 year ago

chLZX commented 1 year ago

When i use spike to simulate SEW=16 vfcvt/vfwcvt instruction, there is always an error,illegal instruction. I want to know that it is the spike bug or i write wrong code.