FLW uses rs1 as integer base ISA

chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification

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FLW uses rs1 as integer base ISA #936

Open dd-baoshan opened 1 year ago

dd-baoshan commented 1 year ago

Floating-point load use the base+offset addressing mode as the integer base ISA, with a base address in register rs1 ad a 12-bit signed byte offset. We need to set has_rs1 at following file for load instruction.