chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
Apache License 2.0
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RVC Instruction gpr coverage collection omissions for CR/CI/CSS formate #942

Open LongStudy opened 1 year ago

LongStudy commented 1 year ago

Hi, when I collecting RVC Instruction coverage, I found that the reg value range of some coverpoints is only gpr[] = {S0, S1, A0, A1, A2, A3, A4, A5}; However, some CR/CI/CSS compression instructions support full register access form X0 to X31, such as c.lwsp and c.swsp.

So I'm considering coverpoint for things like define CL_SP_INSTR_CG_BEGIN(INSTR_NAME) should change from {bins gpr[] = {S0, S1, A0, A1, A2, A3, A4, A5} to { DV(ignore_bins bin = {ZERO} to collect the remaining registers.

I am not sure if my understanding is correct, please point out if there is any problem.