Understanding the Role of UVM and Circuit Simulators

[mutianzh]

Hi,

I'm new to circuit verification and currently learning how to use this tool. From what I understand, the tool can generate randomized instructions, run ISS emulation, and create a trace report to serve as a golden reference. Given that this process doesn't involve circuit simulation, I'm curious—why do we still need UVM and a circuit simulator in this context?

[MikeOpenHWGroup]

why do we still need UVM and a circuit simulator in this context?

Hi @mutianzh, if you ask five verification engineers about this you will get six different answers. :laughing: Here is mine:

• SystemVerilog/UVM is by far the most popular language and methodology for developing verification environments (testbenches) for ASIC and FPGA RTL models used in Industry today. Given that, an SV/UVM implementation of riscv-dv makes sense.
• Once you've got your reference trace report from your ISS, you'll need to generate a trace report through your ASIC/FPGA implementation. Again, the most popular popular language and methodology for that is SV/UVM.

I hope this answers your question. If it does, please close the issue. If you still have questions, you can reach out to me directly (look for me on LinkedIn).