Closed martijnbastiaan closed 6 years ago
Out of interest, do you actually have a design using 9 different clocks?
No, I have yet to design a circuit with more than 2 actually :-). We (me+@christiaanb) settled on just extending it to 9, to prevent a zoo of alteraPll{0,1,2,3,4,5...}
. It shouldn't bother users too much, as Clash 0.99 is backwards incompatible anyway.
Come to think of it.. this PR should probably extend the Xilinx PLLs as well.
@martijnbastiaan If I understand te documentation it seems that for the Stratix series alteraPll
can have up to 18 ports, although it "only" scales up to 9 for the Cyclone series. I don't want to merge this before we have a better solution.
In that case I can see a few options, but none of them seem that great.
alteraPll
, alteraPll9
, and alteraPll18
. A balance between maximum usability, and satisfying ease of use for simple (sample) circuits.KnownNat n => alteraPll n
, where the function will yield a 18-tuple, but only the first n
are usable. This would require some blackbox template magic (which is not possible right now AFAIK). Either we have to introduce more flexible if
statements, or introduce for
loops. Alternatively, we could outsource our templating to, for example, heist or ginger. (Which would also force us to declare all variables used in the template upfront, which would probably be nice. Although this is more a comment on the ergonomics of the current template engine than anything else.)KnownNat n => alteraPll n
, where the function will return a Vec n
. The downside being that all clocks in the vector will need to have the same domain, forcing the user to use unsafe functions to cast clocks to other domains. This would require templating magic similar to (2).alteraPll{1,2,3,4....}
. Lets not do this.
This commits extends alteraPll to include of all of the available 9 output ports.
Should be merged in tandem with: https://github.com/clash-lang/clash-compiler/pull/261