Closed christiaanb closed 6 years ago
So that we can map Bit to std_logic in VHDL, and map BitVector 1 to std_logic_vector(0 downto 0)
Bit
std_logic
BitVector 1
std_logic_vector(0 downto 0)
So that we can map
Bit
tostd_logic
in VHDL, and mapBitVector 1
tostd_logic_vector(0 downto 0)