Configurable RAM sizes for V20x, V30x

[maxgerhardt]

The linker script

https://github.com/cnlohr/ch32v003fun/blob/6c14912e79adf9097d46c3f4688da3b567d64d6c/ch32v003fun/ch32v003fun.ld#L31-L40

for V30x only gives the "256K Flash + 64K RAM" and "128K Flash + 32K RAM" option. This is however wrong: The 128K Flash option doesn't exist naturally. The options for 30x are

And for 20x

Through invocation of the blackest dark magic I've ever seen, flash cells become RAM cells, and their sum is a constant.

Also see https://github.com/Community-PIO-CH32V/platform-ch32v/issues/20 and https://github.com/Community-PIO-CH32V/platform-ch32v/issues/17#issuecomment-1446040078

What I'm specifically saying is that I think the linker script and Makefile is wrong by deducing the "one right" memory sizes only through the chip's name / package name, when in fact, some chips are more freely configurable.

[bmx]

Who's wrong? the datasheet? the linkutility?

[cnlohr]

Through invocation of the blackest dark magic I've ever seen, flash cells become RAM cells, and their sum is a constant.

wat

Can you validate the actual performance?

[maxgerhardt]

Who's wrong? the datasheet? the linkutility?

Ah, indeed I'm wrong, or rather, confusingly worded: The V30x devices marked "256K Flash + 64K SRAM" parts are actually configurable for the 4 options shown in the link utility. This is only the CH32V307(RC/WC/VC) and CH32V303(RC/VC) chips. For the other chips, 303(CB,RB), 305(FB,RB), they do have 128K flash and 32K RAM fixed.

CH32V307DS0.pdf:

For V20x series chips, only V203RB and all V208 have configurable sizes from selections, all others are 32K+10K or 64K+20K.

The point still stands however, V30x sreies chips can actually have 5 different configurations, the .ld file makes only 2 possible.

[cnlohr]

@dwillmore has been postulating that the flash is in fact RAM, and that it's somewhat arbitrary how it's configured. I am extremely curious if we find something like that. It seems that there are bits in the option rom for configuring the bits, see FLASH_OBR

@maxgerhardt would you be up for adding to the .ld file to enable the other forms? Also, it seems you will need to flash the option bytes in order to select between the different modes. Do you have any recommendations on how we could select the appropriate split?

[cnlohr]

Wait... does that mean it can be configured at runtime? I also see it here:

[jnk0le]

Through invocation of the blackest dark magic I've ever seen, flash cells become RAM cells, and their sum is a constant.

wat

@dwillmore has been postulating that the flash is in fact RAM, and that it's somewhat arbitrary how it's configured

This flash is in fact a sram loaded with image from "external" flash, typically done like this: htps://zeptobars.com/en/read/GD32F103CBT6-mcm-serial-flash-Giga-Devices

[dwillmore]

That's a different chip. But I was wondering if they were doing something similar.

On Mon, Apr 22, 2024, 2:30 PM jnk0le @.***> wrote:

Through invocation of the blackest dark magic I've ever seen, flash cells become RAM cells, and their sum is a constant.

wat

@dwillmore https://github.com/dwillmore has been postulating that the flash is in fact RAM, and that it's somewhat arbitrary how it's configured

This flash is in fact a sram loaded with image from "external" flash: htps://zeptobars.com/en/read/GD32F103CBT6-mcm-serial-flash-Giga-Devices https://zeptobars.com/en/read/GD32F103CBT6-mcm-serial-flash-Giga-Devices

— Reply to this email directly, view it on GitHub https://github.com/cnlohr/ch32v003fun/issues/280#issuecomment-2070563892, or unsubscribe https://github.com/notifications/unsubscribe-auth/ACPEX7CMLDWL3WXR3ADABNTY6VJNRAVCNFSM6AAAAABDNYVYCSVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDANZQGU3DGOBZGI . You are receiving this because you were mentioned.Message ID: @.***>

[jnk0le]

someone already decapped it https://cpldcpu.wordpress.com/2024/05/01/decapsulating-the-ch32v203-reveals-a-separate-flash-die/