A few extra patches

[cpitclaudel]

I've added details in the individual commits. Let me know if you want me to write matching tests.

[acw1251]

Thanks, these look good. I'm writing some tests for these myself since I've never used plus args before in Verilog.

There are a few changes I'm going to make when I merge this if that's okay with you. I'm going to renameverilator_defines to verilog_defines, and I'm going to make verilog_defines be a list of strings instead of a list of tuples. This allows you to define macros without values by just adding "MACRO" to verilog_defines and macros with values by adding "MACRO=value". This will look very similar to adding plus args to command_args

I'll merge this once the tests are done and I'm ready to make my changes to it as well.

[cpitclaudel]

I'm going to renameverilator_defines to verilog_defines, and I'm going to make verilog_defines be a list of strings instead of a list of tuples.

That's a very good idea :+1: Thanks a lot for the quick review!

[cpitclaudel]

Re. plusargs, this is how I use them in BRAM2BELoad:

`ifdef BRAM_RUNTIME_INIT
   wire[8 * 256 - 1:0] filename;

   initial
     begin : init_rom_block
      if ($value$plusargs("VMH=%s", filename)) begin
         $readmemh(filename, RAM, 0, MEMSIZE-1);
      end else begin
         $fwrite(32'h80000002, "ERROR: No memory image loaded. Use +VMH=<path> to load one\n");
         $finish(1'b1);
      end
   end
`else
   initial
     begin : init_rom_block
        $readmemh("mem.vmh", RAM, 0, MEMSIZE-1);
     end
`endif

And I set BRAM_RUNTIME_INIT on the command line