PLA

[patzik]

Not really an issue, but could you add the xsvf file to the repo? Makes programming a bit easier for me.

[desaster]

I haven't actually used .xsvf myself, since I'm using a bit hacky way of programming the device with .svf and busblaster.

With a bit of confused clicking around in ISE iMPACT (I don't use xilinx tools very often), I managed to create an .xsvf file. I've attached it here for your convenience. I have no idea if it works, though.

dodgypla_xsvf.zip

As for including it in in the repo, I'll give it some consideration. I'm usually against including compiled output among the source code, but maybe it could be shared as a release.

[patzik]

I am trying to program it with an ever hackier way :-) I programmed a stm32 ‘bluepill’ board, to program the xc9536xl chip. Never tried it before and am having some problems. Don’t know where the problem lies, too many ‘new’ things in this process. We’ll see how I get along. Could be a 2euro sollution to program it :-)

Verstuurd vanaf mijn iPhone

Op 4 jun. 2018 om 19:38 heeft desaster notifications@github.com het volgende geschreven:

I haven't actually used .xsvf myself, since I'm using a bit hacky way of programming the device with .svf and busblaster.

With a bit of confused clicking around in ISE iMPACT (I don't use xilinx tools very often), I managed to create an .xsvf file. I've attached it here for your convenience. I have no idea if it works, though.

dodgypla_xsvf.zip

As for including it in in the repo, I'll give it some consideration. I'm usually against including compiled output among the source code, but maybe it could be shared as a release.

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub, or mute the thread.

[desaster]

Here are my notes about working with xilinx. The last parts might be interesting to you, since you're also doing a hacky way.

Creating new project

Name: asdasd Location: /home/desaster/projects/fpga/xilinx/asdasd Working Directory /home/desaster/projects/fpga/xilinx/asdasd (a folder will be created under this directory)

Device: XC9536XL Package: VQ44 Speed: (check the chip?)

Creating top level entity

Right click asdasd -> New Source Verilog Module File Name: asdasd

Add code, for example:

`timescale 1ns / 1ps

module ledblink(clk, LED);

input clk;
output LED;

reg [32:0] cnt;
always @(posedge clk) cnt <= cnt + 1;
assign LED = cnt[23];

Right click asdasd.v -> Set as top module

If code and everything is ok, "Implement Design" appears in design tab. Can run Synthetize now for test.

Pin Assignment

Right click asdasd -> New Source -> Implementation Constraints File File Name: pins

Add pin assignments, for example:

NET "clk" LOC = "P1";
NET "LED" LOC = "P32";

After this, the following steps should work:

• Synthesize
• Translate
• Fit
• Generate Programming File

Generating SVF for programming

Design -> Configure Target Device

This starts iMPACT

File -> new

This pops up Welcome to iMPACT, where you can select: Prepare Boundary-Scan File (SVF)

Choose an .svf file where all operations will be saved Then select the previously generated .jed file

Double click Boundary Scan

Right click on the device -> Program (if the programming properties are ok, then this should also erase and verify)

Output -> SVF File -> Stop writing to output

Programming the SVF file using Bus Blaster

Before programming the the file, the SVF file needs to have it's freqency changed. Find the line with FREQUENCY and change 1E6 to 3E5

sudo /usr/local/bin/jtag

cable jtagkey vid=0x403 pid=0x6010 interface=0

If this fails, urjtag is built using libftd2xx and you need to run:

sudo rmmod ftdi_sio

When the cable command is ok, run:

detect

This should provide no errors:

jtag> detect IR length: 8 Chain length: 1 Device Id: 01011001011000000010000010010011 (0x59602093) Manufacturer: Xilinx (0x093) Part(0): xc9536xl (0x9602) Stepping: 5 Filename: /usr/local/share/urjtag/xilinx/xc9536xl/xc9536xl_vq44

If there is an error:

Unknown stepping! (0101) (/usr/local/share/urjtag/xilinx/xc9536xl/STEPPINGS)

Then you need to add the device to the STEPPINGS file:

0101 xc9536xl_vq44 5

If detect went okay, then you can program the file:

svf ~/projects/fpga/xilinx/asdasd/asdasd.svf stop progress

(Don't forget to add the stop and progress parameters)

Successful programming outputs:

detail: Parsing 5160/5163 ( 99%)detail: detail: Scanned device output matched expected TDO values.

[patzik]

I realized I have an altera usb blaster lying here, and I might be able to use it with urjtag to program an sfv file. Can I ask you for the sfv file ;-)

On 4 Jun 2018, at 20:18, desaster notifications@github.com wrote:

Here are my notes about working with xilinx. The last parts might be interesting to you, since you're also doing a hacky way.

Creating new project

Name: asdasd Location: /home/desaster/projects/fpga/xilinx/asdasd Working Directory /home/desaster/projects/fpga/xilinx/asdasd (a folder will be created under this directory)

Device: XC9536XL Package: VQ44 Speed: (check the chip?)

Creating top level entity

Right click asdasd -> New Source Verilog Module File Name: asdasd

Add code, for example:

`timescale 1ns / 1ps

module ledblink(clk, LED);

input clk; output LED;

reg [32:0] cnt; always @(posedge clk) cnt <= cnt + 1; assign LED = cnt[23]; Right click asdasd.v -> Set as top module

If code and everything is ok, "Implement Design" appears in design tab. Can run Synthetize now for test.

Pin Assignment

Right click asdasd -> New Source -> Implementation Constraints File File Name: pins

Add pin assignments, for example:

NET "clk" LOC = "P1"; NET "LED" LOC = "P32"; After this, the following steps should work:

Synthesize Translate Fit Generate Programming File Generating SVF for programming

Design -> Configure Target Device

This starts iMPACT

File -> new

This pops up Welcome to iMPACT, where you can select: Prepare Boundary-Scan File (SVF)

Choose an .svf file where all operations will be saved Then select the previously generated .jed file

Double click Boundary Scan

Right click on the device -> Program (if the programming properties are ok, then this should also erase and verify)

Output -> SVF File -> Stop writing to output

Programming the SVF file using Bus Blaster

Before programming the the file, the SVF file needs to have it's freqency changed. Find the line with FREQUENCY and change 1E6 to 3E5

sudo /usr/local/bin/jtag

cable jtagkey vid=0x403 pid=0x6010 interface=0

If this fails, urjtag is built using libftd2xx and you need to run:

sudo rmmod ftdi_sio

When the cable command is ok, run:

detect

This should provide no errors:

jtag> detect IR length: 8 Chain length: 1 Device Id: 01011001011000000010000010010011 (0x59602093) Manufacturer: Xilinx (0x093) Part(0): xc9536xl (0x9602) Stepping: 5 Filename: /usr/local/share/urjtag/xilinx/xc9536xl/xc9536xl_vq44

If there is an error:

Unknown stepping! (0101) (/usr/local/share/urjtag/xilinx/xc9536xl/STEPPINGS)

Then you need to add the device to the STEPPINGS file:

0101 xc9536xl_vq44 5

If detect went okay, then you can program the file:

svf ~/projects/fpga/xilinx/asdasd/asdasd.svf stop progress

(Don't forget to add the stop and progress parameters)

Successful programming outputs:

detail: Parsing 5160/5163 ( 99%)detail: detail: Scanned device output matched expected TDO values.

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/desaster/c64-dodgypla/issues/1#issuecomment-394449866, or mute the thread https://github.com/notifications/unsubscribe-auth/Ae1bLl_SifkEMsKyyPIHyDMMuuOLmKEdks5t5Xn1gaJpZM4UZXfb.

[patzik]

I am getting close, I got the usbblaster to recognize the xc9536xl with urjtag, now I only need the svf file to program it. I know I should be able to make it myself from the source, but I don't have ISE at the moment due to a HD crash. And downloading/installing it just for this is more work than just asking you nicely.. :-)

2018-06-04 21:44 GMT+02:00 Patrick Kerkhof patzik@gmail.com:

I realized I have an altera usb blaster lying here, and I might be able to use it with urjtag to program an sfv file. Can I ask you for the sfv file ;-)

On 4 Jun 2018, at 20:18, desaster notifications@github.com wrote:

Here are my notes about working with xilinx. The last parts might be interesting to you, since you're also doing a hacky way. Creating new project

Name: asdasd Location: /home/desaster/projects/fpga/xilinx/asdasd Working Directory /home/desaster/projects/fpga/xilinx/asdasd (a folder will be created under this directory)

Device: XC9536XL Package: VQ44 Speed: (check the chip?) Creating top level entity

Right click asdasd -> New Source Verilog Module File Name: asdasd

Add code, for example:

`timescale 1ns / 1ps

module ledblink(clk, LED);

input clk; output LED;

reg [32:0] cnt; always @(posedge clk) cnt <= cnt + 1; assign LED = cnt[23];

Right click asdasd.v -> Set as top module

If code and everything is ok, "Implement Design" appears in design tab. Can run Synthetize now for test. Pin Assignment

Right click asdasd -> New Source -> Implementation Constraints File File Name: pins

Add pin assignments, for example:

NET "clk" LOC = "P1"; NET "LED" LOC = "P32";

After this, the following steps should work:

• Synthesize
• Translate
• Fit
• Generate Programming File

Generating SVF for programming

Design -> Configure Target Device

This starts iMPACT

File -> new

This pops up Welcome to iMPACT, where you can select: Prepare Boundary-Scan File (SVF)

Choose an .svf file where all operations will be saved Then select the previously generated .jed file

Double click Boundary Scan

Right click on the device -> Program (if the programming properties are ok, then this should also erase and verify)

Output -> SVF File -> Stop writing to output Programming the SVF file using Bus Blaster

Before programming the the file, the SVF file needs to have it's freqency changed. Find the line with FREQUENCY and change 1E6 to 3E5

sudo /usr/local/bin/jtag

cable jtagkey vid=0x403 pid=0x6010 interface=0

If this fails, urjtag is built using libftd2xx and you need to run:

sudo rmmod ftdi_sio

When the cable command is ok, run:

detect

This should provide no errors:

jtag> detect IR length: 8 Chain length: 1 Device Id: 01011001011000000010000010010011 (0x59602093) Manufacturer: Xilinx (0x093) Part(0): xc9536xl (0x9602) Stepping: 5 Filename: /usr/local/share/urjtag/xilinx/xc9536xl/xc9536xl_vq44

If there is an error:

Unknown stepping! (0101) (/usr/local/share/urjtag/ xilinx/xc9536xl/STEPPINGS)

Then you need to add the device to the STEPPINGS file:

0101 xc9536xl_vq44 5

If detect went okay, then you can program the file:

svf ~/projects/fpga/xilinx/asdasd/asdasd.svf stop progress

(Don't forget to add the stop and progress parameters)

Successful programming outputs:

detail: Parsing 5160/5163 ( 99%)detail: detail: Scanned device output matched expected TDO values.

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/desaster/c64-dodgypla/issues/1#issuecomment-394449866, or mute the thread https://github.com/notifications/unsubscribe-auth/Ae1bLl_SifkEMsKyyPIHyDMMuuOLmKEdks5t5Xn1gaJpZM4UZXfb .

[patzik]

I did install Xilinx ISE and generate a svf myself. I assume I did it correct but I can’t seem to be able to program it.

I keep getting this error:

Warning: USB-Blaster frequency is fixed to 12000000 Hz Error svf: mismatch at position 17 for TDO in input file between line 41 col 1 and line 41 col 49 Error occurred for SVF command SDR. Parsing 8500/8506 ( 99%) Mismatches occurred between scanned device output and expected TDO values.

I’m lost at this point, any suggestions?

On 4 Jun 2018, at 20:18, desaster notifications@github.com wrote:

Here are my notes about working with xilinx. The last parts might be interesting to you, since you're also doing a hacky way.

Creating new project

Name: asdasd Location: /home/desaster/projects/fpga/xilinx/asdasd Working Directory /home/desaster/projects/fpga/xilinx/asdasd (a folder will be created under this directory)

Device: XC9536XL Package: VQ44 Speed: (check the chip?)

Creating top level entity

Right click asdasd -> New Source Verilog Module File Name: asdasd

Add code, for example:

`timescale 1ns / 1ps

module ledblink(clk, LED);

input clk; output LED;

reg [32:0] cnt; always @(posedge clk) cnt <= cnt + 1; assign LED = cnt[23]; Right click asdasd.v -> Set as top module

If code and everything is ok, "Implement Design" appears in design tab. Can run Synthetize now for test.

Pin Assignment

Right click asdasd -> New Source -> Implementation Constraints File File Name: pins

Add pin assignments, for example:

NET "clk" LOC = "P1"; NET "LED" LOC = "P32"; After this, the following steps should work:

Synthesize Translate Fit Generate Programming File Generating SVF for programming

Design -> Configure Target Device

This starts iMPACT

File -> new

This pops up Welcome to iMPACT, where you can select: Prepare Boundary-Scan File (SVF)

Choose an .svf file where all operations will be saved Then select the previously generated .jed file

Double click Boundary Scan

Right click on the device -> Program (if the programming properties are ok, then this should also erase and verify)

Output -> SVF File -> Stop writing to output

Programming the SVF file using Bus Blaster

Before programming the the file, the SVF file needs to have it's freqency changed. Find the line with FREQUENCY and change 1E6 to 3E5

sudo /usr/local/bin/jtag

cable jtagkey vid=0x403 pid=0x6010 interface=0

If this fails, urjtag is built using libftd2xx and you need to run:

sudo rmmod ftdi_sio

When the cable command is ok, run:

detect

This should provide no errors:

jtag> detect IR length: 8 Chain length: 1 Device Id: 01011001011000000010000010010011 (0x59602093) Manufacturer: Xilinx (0x093) Part(0): xc9536xl (0x9602) Stepping: 5 Filename: /usr/local/share/urjtag/xilinx/xc9536xl/xc9536xl_vq44

If there is an error:

Unknown stepping! (0101) (/usr/local/share/urjtag/xilinx/xc9536xl/STEPPINGS)

Then you need to add the device to the STEPPINGS file:

0101 xc9536xl_vq44 5

If detect went okay, then you can program the file:

svf ~/projects/fpga/xilinx/asdasd/asdasd.svf stop progress

(Don't forget to add the stop and progress parameters)

Successful programming outputs:

detail: Parsing 5160/5163 ( 99%)detail: detail: Scanned device output matched expected TDO values.

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/desaster/c64-dodgypla/issues/1#issuecomment-394449866, or mute the thread https://github.com/notifications/unsubscribe-auth/Ae1bLl_SifkEMsKyyPIHyDMMuuOLmKEdks5t5Xn1gaJpZM4UZXfb.

[desaster]

Hmm no idea really, all I can guess is that the frequency is too high, since I also had to change that manually.

I believe I didn't have to use external pull-ups for the pins, but that might be worth a shot.

[patzik]

There might be a problem with the svf file I generated, could you mail me the svf file you used so I can see if it is different? I can id the chip via the jtag, so it is working….

On 5 Jun 2018, at 06:44, desaster notifications@github.com wrote:

Hmm no idea really, all I can guess is that the frequency is too high, since I also had to change that manually.

I believe I didn't have to use external pull-ups for the pins, but that might be worth a shot.

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/desaster/c64-dodgypla/issues/1#issuecomment-394579919, or mute the thread https://github.com/notifications/unsubscribe-auth/Ae1bLrn1V2vVyL2a_cpzvF0yL-HkVZiaks5t5gyRgaJpZM4UZXfb.

[desaster]

Attached is the svf file. There's nothing special about it though, except for the changed frequency.

dodgypla_svf.zip

[patzik]

Well, the svf I generated is exactly the same, so that wasn't the issue. Out comes programming option number 3... It just happens I was building an easyflash3 cartridge this week, and realized it also has a Xilinx chip on it which I had to program. This cartridge has an "onboard solution' for this. So I thought why not use the jtag pins from this cartridge and program the pla this way. It's a bit of a hack, but hey it's free! Worked like a charm :-) Thanks for your help, I'll upload a picture soon.

[patzik]

Here's the picture ;-)

[mamejay]

Hello patzik. I have an easy flash 3 cart the same as yours. I want to do the same hack as yourself. Do I still use the same process as programming the EF3 using the following command? Also do I still need to connect the cart to the C64 as well as the USB of the PC? easp -p 0x8738 -v

[patzik]

Yes the procedure is exactly the same as flashing the onboard chip. So with cart connected to the c64, and c64 has to be on. I use a different board design so make sure you check the connections.

[mamejay]

Just to confirm this is the EF3 pinout. Also are the programming pins the middle row? Its hard to tell due to reflection that is in your picture.

[patzik]

It’s the 4 pins of the middle row, and the gnd+vcc from the top row

[mamejay]

Got it all working last night. Hooked up my chip adapter to a breadboard so I could program them out of circuit and it all worked. Thanks so much for your help. Now just waiting on some caps to finish the build.