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desaster / c64-dodgypla

Commodore 64 PLA replacement
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Severe audio glitches with Nano SwinSID in some boards? #4

Closed modeler closed 4 years ago

modeler commented 4 years ago

I have a 250407 Rev. B board with DodgyPLA (actually the hackup.net variant XCPLA) and Nano SwinSID. This combination of PLA and SID works fine in other boards, but in one board I get very crackly and distorted audio.

If I replace either of these, e.g. swap the SwinSID for ARMSID or swap the XCPLA for PLAnkton, the problem goes away. It is only this combination and only this particular board. I have other 250407 boards that are not affected. Has anyone else had this problem at all? I am not looking for a fix, but it would be nice to have some idea of why PLAnkton doesn't suffer from this.

1c3d1v3r commented 4 years ago

I fixed this issue in my fork neatPLA https://github.com/1c3d1v3r/neatPLA It's an easy fix. Add delay to all output ports. I implemented it by just inverting the signals twice. CASRAM delay could be expanded at the same time. 30ns works perfect. DodgyPLA got now 20ns which is too short for some oldest motherboards. Notice neatPLA got different pinout than dodgyPLA.

desaster commented 4 years ago

Great that you've found a fix. The ~20ns CASRAM delay is directly based on a range in skoe's document, and I chose the average of that for most compatibility. I guess in real life it might not always be the best delay.

Adding delay to all output ports is curious. Were both CASRAM delay + all pins delay necessary for this fix?

I wonder if settings pins to slow slew rate would help with this - IIRC for now I've only enable it on CASRAM.

PS. I should probably add links to XCPLA & neatPLA in README, and keep my project as a sort of a reference design.

1c3d1v3r commented 4 years ago

IIRC PLAnkton got even 40ns CASRAM delay.

CASRAM delay was increased to 30ns for old MB compatibility. Delay to all other pins fixed the SwinSID issue. 30ns CASRAM was already implemented when testing this.

Just by using dodgypla_core.v from neatPLA should fix all issues since the delays are in that code. This is independent from the pinout change which is in pins.ucf file.

modeler commented 4 years ago

Thank you both! hackup.net provided an SVF file for use with OpenOCD, which is what I used to program my XCPLAs (using a Raspberry Pi as a JTAG programmer). I will see if I can generate an updated SVF using the project files from neatPLA.

Unable to test immediately but will close the issue as this looks pretty conclusive to me.

modeler commented 4 years ago

I was able to take dodgypla_core.v from neatPLA as suggested and generate a new JED file with Xilinx ISE, then made an updated SVF with the delays implemented. This does indeed fix the problem with SwinSID in my board, thank you.

Made a fork of hackup.net's repo with these files in place of the originals, should anyone need them: https://github.com/modeler/c64-dodgypla