[ ] test_single_port_mem/nlmeans_simple_trunc (skip, tb size needs to be 4)
[ ] test_pond/nlmeans_simple (skip, tb size needs to be 4)
[ ] test_pond/three_level_pond_rolled (skip, in2agg dim = 4)
Clockwork changes TODO:
[ ] prioritize the initialization path in the update operation so that the Agg2Sram doing initialization will always write to SRAM right after it receives 4 words (refer to output bank 6 in resnet_init_unroll_tile)
[ ] (probably related to the issue above) prioritize Agg2Sram in normal operations so it writes SRAM right after it receives 4 words (refer to ub_hw_input_global_wrapper_stencil_BANK_0 in matmul_unroll2)
[x] linearize Agg2Sram read and write data strides (refer to camera_pipeline_2x2)
[ ] (probably related to the change above) remove Agg2Sram read_data_starting_addr and write_data_starting_addr as they should always be 0. Can also remove In2Agg write_data_starting_addr for the same reason
[ ] (optional): flatten In2Agg ID as much as possible (this is currently done in Lake and we are using maximum 3 ID levels)
Lake Changes:
[x] update LakeTop wrapper with the options to configure and enable/disable the area optimizations
[ ] remove linearization pass in Lake once they are done in clockwork
[ ] (optional) remove flatten pass in Lake once they are done in clockwork
Missing compute unit file:
Current Failed tests:
Skipped Tests:
Clockwork changes TODO:
resnet_init_unroll_tile
)ub_hw_input_global_wrapper_stencil_BANK_0
inmatmul_unroll2
)camera_pipeline_2x2
)read_data_starting_addr
andwrite_data_starting_addr
as they should always be 0. Can also remove In2Aggwrite_data_starting_addr
for the same reasonLake Changes: