Closed legden closed 6 years ago
Optimizations for Xilinx's platform is under going. The upcoming new version will be released by the end of this month. We will do our best to provide the best design for both vendors, althought it is really difficult.
@legden Hi please check out the latest update. We have add support for SDAccel.
conv_pipe.cl is heavily depend on altera specific extensions (write_channel_altera, read_channel_altera), so it can't be compiled to use with xilinx FPGAs.