This repository is the GF180MCU port of management core for Caravel. For more information about the Caravel management SoC, see https://github.com/efabless/caravel_mgmt_soc_litex.
The caravel_core layout makes reference to a cell called gf180_ram_512x8_wrapper which does not exist in any view. This makes it impossible to read the SoC layout into magic, and makes it impossible to run LVS on the caravel top level.
The
caravel_core
layout makes reference to a cell calledgf180_ram_512x8_wrapper
which does not exist in any view. This makes it impossible to read the SoC layout into magic, and makes it impossible to run LVS on the caravel top level.