The Great Unit Test Tracker

[donn]

Misc Unit Tests

• [ ] pdk_compat.py

[kareefardi]

Step Unit Tests

• General case:
  • [ ] success
  • [ ] failure:
    • [ ] bad input
    • [ ] bad configuration. e.g. floorplan impossible util...
  • [ ] reproducibles that are fixed
• [x] Checker.DisconnectedPins
• [x] Checker.IllegalOverlap
• [x] Checker.LVS
• [x] Checker.LintErrors
• [x] Checker.LintTimingConstructs https://github.com/efabless/openlane2/pull/233
  • [x] fail
  • [x] success
  • [x] not found
• [x] Checker.LintWarnings
• [x] Checker.MagicDRC
• [x] Checker.TrDRC
• [x] Checker.WireLength https://github.com/efabless/openlane2/pull/233
  • [x] fail
  • [x] success
  • [x] not found
• [x] Checker.XOR
• [x] Checker.YosysChecks
• [x] Checker.YosysUnmappedCells - [ ] KLayout.OpenGUI (xvfb breaks 80 times a second im not testing this)
• [x] KLayout.Render
  • [x] success comparison with a known png
  • [x] fail - bad DEF.
• [x] KLayout.StreamOut
  • [x] success no macros
  • [x] success macros only
  • [x] success hybrid (macros + std cells)
  • [x] fail bad DEF.
• [x] KLayout.XOR
  • [x] success
  • [x] fail xor
  • [x] fail bad GDS
  • [ ] multithread option - check speed ?? (blocked #234)
  • [x] ignore layers option. True XOR in an ignored layer reporting clean XOR.
• [ ] Magic.DRC https://github.com/efabless/openlane2/pull/233
  • [x] true positive - there are DRC errors with GDS
  • [x] true positive - there are DRC errors with DEF-LEF
  • [x] true negative - no DRC errors with GDS
  • [ ] true negative - no DRC errors with DEF-LEF. Blocked on https://github.com/RTimothyEdwards/open_pdks/issues/410
  • [ ] fail bad DEF.
  • [ ] fail bad LEF.
  • [ ] fail bad GDS.
• [ ] Magic.SpiceExtraction - Skipping this for now. Since there is no obvious way to verify the generated spice file.
  • NOTE: MAGIC_NO_EXT_UNIQUE - JC (user) test case add to integartion tests - a design
  • [ ] success using GDS
  • [ ] success using DEF
  • [ ] success with IllegalOverlap
• [x] Magic.StreamOut https://github.com/efabless/openlane2/pull/233
  • [x] success no macros
  • [x] success macros only
  • [x] success hybrid (macros + std cells)
  • [x] success hybrid - Magic macro std cell source = PDK
  • [x] fail bad GDS
  • [x] fail bad DEF.
• [x] Magic.WriteLEF https://github.com/efabless/openlane2/pull/233
  • [x] Abstract and full
    • [x] def
    • [x] def hybrid
    • [x] GDS
    • [x] GDS hybrid
  • [x] bad input DEF
  • [x] bad input LEF
  • [x] bad input GDS
• [ ] Misc.LoadBaseSDC
• [ ] Netgen.LVS
  • [ ] pass
  • [ ] pass blackbox
  • [ ] pass full
  • fail on each of the following:
    • [ ] designlvs_device_differencecount
    • [ ] designlvs_net_differencescount
    • [ ] designlvs_property_failscount
    • [ ] design__lvs_errors__count
    • [ ] designlvs_unmatched_devicescount
    • [ ] designlvs_unmatched_netscount
    • [ ] designlvs_unmatched_pinscount
  • fail bad spice
  • fail bad verilog
• [x] Odb.ApplyDEFTemplate https://github.com/efabless/openlane2/pull/250
  • [x] success
  • [x] bad input DEF
  • [x] mismatching input DEF
• [x] Odb.CustomIOPlacement https://github.com/efabless/openlane2/pull/250
  • [x] success
  • [x] fail due to umatched pins
  • [x] fail due to bad input odb
  • [x] fail due to bad configuration file. There are multiple ways in which the configuration file can be bad. TBD point of failures in the configuration file.
• [ ] Odb.DiodesOnPorts: Waiting for https://github.com/efabless/openlane2/pull/255
  • [ ] success on in
  • [ ] success on out
  • [ ] success on both
  • [ ] skip on none
  • [ ] fail on bad DIODE_CELL config - multiple points of failure
  • [ ] fail on bad odb
• [ ] Odb.HeuristicDiodeInsertion: Waiting for https://github.com/efabless/openlane2/pull/255
  • [ ] success on different threshold values
  • [ ] fail on bad odb
  • [ ] fail on bad DIODE_CELL config - multiple points of failure
• [ ] Odb.ManualMacroPlacement
  • [ ] success
  • [ ] fail bad odb
  • [ ] fail misconfigured MACRO object - potential enhancement ??
  • no need to test cfg file as it is under deprecation.
• [ ] Odb.ReportDisconnectedPins
  • [ ] positive disconnected power and signal pins
  • [ ] fail bad odb
• [ ] Odb.ReportWireLength
  • [ ] success
  • [ ] success no wires in odb
  • [ ] fail bad odb
• [ ] OpenROAD.BasicMacroPlacement
  • Not implemented ??
• [ ] OpenROAD.CTS
  • [ ] CTS is sensitive to SDC
  • [ ] There seems to be alot of configuration paramters for CTS. I am not entierly sure yet what would be a strategy to test all of them
  • [ ] success multiple clocks
  • [ ] success multiple generated clocks
  • [ ] success single clock
  • [ ] success no clock
  • [ ] fail bad odb
• [ ] OpenROAD.CheckAntennas https://github.com/efabless/openlane2/pull/244
  • [x] success no violations
  • [x] success violations
  • [x] fail no routes
  • [ ] fail bad odb
• [ ] OpenROAD.CheckSDCFiles
• [ ] OpenROAD.DetailedPlacement
  • [x] fail no space -> over exagerate padding https://github.com/efabless/openlane2/pull/244
  • [x] fail no space -> resonable padding util > 100% https://github.com/efabless/openlane2/pull/244
  • [ ] fail max displacement x - TBD
  • [ ] fail max displacement y - TBD
  • [ ] success max displacement x - TBD
  • [ ] success max displacement y - TBD
  • [x] success https://github.com/efabless/openlane2/pull/244
  • [ ] fail bad odb
• [ ] OpenROAD.DetailedRouting https://github.com/efabless/openlane2/pull/244
  • [x] fail too little iterations
  • [x] fail layer (min) in guide not accessible
  • [x] fail layer (max) in guide not accessible
  • [x] fail pin not accessible
  • [ ] fail no access obs
  • [x] success
  • [x] success assert 1 thread
  • [x] success assert 4 thread
  • [ ] fail bad odb
• [x] OpenROAD.FillInsertion https://github.com/efabless/openlane2/pull/244
  • [x] fail bad filler cell
  • [x] ~fail~ success no space
  • [x] success
  • [ ] fail bad odb
• [ ] OpenROAD.Floorplan https://github.com/efabless/openlane2/pull/244
  • [x] success relative
  • [x] success aboslute
  • [x] success 0 margin
  • [x] fail -ve margin
  • [x] fail -ve utilization
  • [x] fail margin > area
  • [ ] fail bad aspect ration
  • [ ] test insert_tiecells
  • [ ] test impossible dimensions - TBD. Two points passed to die area are treated as bbox points. Hence there is no impossible dimension (maybe 0,0,0,0). However a diea area set to "DIE_AREA": "0 100 34.5 57.12" results in a bbox of 0.0 57.12 34.5 100.0. This can be considered a user error and should be captured.
  • [ ] fail bad netlist
• [ ] OpenROAD.GeneratePDN
• [ ] OpenROAD.GlobalPlacement https://github.com/efabless/openlane2/pull/244
  • [x] success
  • [x] success time driven only
  • [x] success routability driven only
  • [x] success skip-initial-place
  • [x] success no timing no routability
  • [x] fail high util
  • [x] fail high padding (results in high util)
• [ ] OpenROAD.GlobalPlacementSkipIO
• [ ] OpenROAD.GlobalRouting
• [ ] OpenROAD.IOPlacement https://github.com/efabless/openlane2/pull/244
  • [ ] Pin geometry options: https://github.com/efabless/openlane2/issues/253
  • [x] success matching
  • [x] success random
  • [x] fail bad metal layer
• [ ] OpenROAD.IRDropReport
• [ ] OpenROAD.LayoutSTA
• [ ] OpenROAD.OpenGUI
• [ ] OpenROAD.RCX https://github.com/efabless/openlane2/pull/244
  • [x] Success simple design
  • [x] Success simple macro
  • [x] Success macro + design level std cells
  • [x] Success no_merge_via_res Success is measured by reading in the generated spef file and report unannotated wires.
• [ ] OpenROAD.RepairDesign
• [ ] OpenROAD.RepairDesignPostGPL
• [ ] OpenROAD.RepairDesignPostGRT
• [ ] OpenROAD.ResizerTimingPostCTS
• [ ] OpenROAD.ResizerTimingPostGRT
• [ ] OpenROAD.STAMidPNR
• [ ] OpenROAD.STAPostPNR
• [ ] OpenROAD.STAPrePNR
• [ ] OpenROAD.TapEndcapInsertion https://github.com/efabless/openlane2/pull/244
  • [x] Success
  • [x] Fail large distance / small area
  • [x] Fail bad master cells
• [ ] Verilator.Lint
• [ ] Yosys.EQY
• [ ] Yosys.JsonHeader
• [ ] Yosys.Synthesis